place: added few comments and removed compile warning

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/physical_types.h

@@ -652,7 +652,6 @@ struct t_physical_tile_port {
     int index;
     int absolute_first_pin_index;
     int port_index_by_type;
-    int tile_type_index;
 };
 
 /* Describes the type for a logical block

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -878,8 +878,6 @@ static std::pair<int, int> ProcessPinString(pugi::xml_node Locations,
     VTR_ASSERT(port != nullptr);
     int abs_first_pin_idx = port->absolute_first_pin_index;
 
-    std::pair<int, int> pins;
-
     token_index++;
 
     // All the pins of the port are taken or the port has a single pin
@@ -3245,7 +3243,7 @@ static void ProcessEquivalentSiteDirects(pugi::xml_node Parent,
 
     if (count_children(Parent, "direct", loc_data) < 1) {
         archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
-                       "There are no direct pin mappings between site %s and tile %s.\n", site_name, PhysicalTileType->name);
+                       "There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), PhysicalTileType->name);
     }
 
     std::unordered_map<int, int> directs_map;
@@ -3257,10 +3255,12 @@ static void ProcessEquivalentSiteDirects(pugi::xml_node Parent,
         expect_only_attributes(CurDirect, {"from", "to"}, loc_data);
 
         std::string from, to;
+        // `from` attribute is relative to the physical tile pins
         from = std::string(get_attribute(CurDirect, "from", loc_data).value());
+
+        // `to` attribute is relative to the logical block pins
         to = std::string(get_attribute(CurDirect, "to", loc_data).value());
 
-        // XXX
         auto from_pins = ProcessPinString<t_physical_tile_type_ptr>(CurDirect, PhysicalTileType, from.c_str(), loc_data);
         auto to_pins = ProcessPinString<t_logical_block_type_ptr>(CurDirect, LogicalBlockType, to.c_str(), loc_data);
 

vpr/src/base/clustered_netlist.h

@@ -255,8 +255,10 @@ class ClusteredNetlist : public Netlist<ClusterBlockId, ClusterPortId, ClusterPi
     //Pins
     vtr::vector_map<ClusterPinId, int> pin_physical_index_; //The physical pin index (i.e. pin index
                                                             //in t_physical_tile_type) corresponding
-                                                            //to the logical pin
-    vtr::vector_map<ClusterPinId, int> pin_logical_index_;  //The logical pin index of this block
+                                                            //to the clustered pin
+    vtr::vector_map<ClusterPinId, int> pin_logical_index_;  //The logical pin index of this block (i.e. pin index
+                                                            //in t_logical_block_type) corresponding
+                                                            //to the clustered pin
 
     //Nets
     vtr::vector_map<ClusterNetId, bool> net_is_ignored_; //Boolean mapping indicating if the net is ignored