Change t_pb_type users to use helper functions

Author: AmirhosseinPoolad

libs/libarchfpga/src/arch_util.cpp

@@ -1077,7 +1077,7 @@ bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& bl
 
     if (pb_type->blif_model != nullptr) {
         //Leaf pb_type
-        VTR_ASSERT(pb_type->num_modes == 0);
+        VTR_ASSERT(pb_type->is_primitive());
         if (blif_model_name == pb_type->blif_model
             || ".subckt " + blif_model_name == pb_type->blif_model) {
             return true;

libs/libarchfpga/src/physical_types.h

@@ -1361,7 +1361,7 @@ class t_pb_graph_node {
     t_interconnect_pins** interconnect_pins; /* [0..num_modes-1][0..num_interconnect_in_mode] */
 
     // Returns true if this pb_graph_node represents a primitive type (primitives have 0 modes)
-    bool is_primitive() const { return this->pb_type->num_modes == 0; }
+    bool is_primitive() const { return this->pb_type->is_primitive(); }
 
     // Returns true if this pb_graph_node represents a root graph node (ex. clb)
     bool is_root() const { return this->parent_pb_graph_node == nullptr; }

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -1415,7 +1415,7 @@ static void ProcessPb_Type(pugi::xml_node Parent,
         pb_type->pb_type_power->leakage_default_mode = 0;
         int mode_idx = 0;
 
-        if (pb_type->num_modes == 0) {
+        if (pb_type->is_primitive()) {
             /* The pb_type operates in an implied one mode */
             pb_type->num_modes = 1;
             pb_type->modes = new t_mode[pb_type->num_modes];

vpr/src/analytical_place/flat_placement_mass_calculator.cpp

@@ -68,7 +68,7 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) {
     // capacities as if the pb could choose either one.
     PrimitiveVector capacity;
     // If this is a leaf / primitive, create the base PrimitiveVector capacity.
-    if (pb_type->num_modes == 0) {
+    if (pb_type->is_primitive()) {
         LogicalModelId model_id = pb_type->model_id;
         VTR_ASSERT(model_id.is_valid());
         capacity.add_val_to_dim(get_model_mass(model_id), (size_t)model_id);

vpr/src/base/read_netlist.cpp

@@ -463,7 +463,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p
         VTR_ASSERT(clb_nlist->block_ports(index).size() == (unsigned)pb_type->num_ports);
     }
 
-    if (pb_type->num_modes == 0) {
+    if (pb_type->is_primitive()) {
         /* A primitive type */
         AtomBlockId blk_id = atom_ctx.netlist().find_block(pb->name);
         if (!blk_id) {

vpr/src/draw/intra_logic_block.cpp

@@ -202,8 +202,8 @@ static int draw_internal_find_max_lvl(const t_pb_type& pb_type) {
     t_mode mode;
     int max_levels = 0;
 
-    /* If no modes, we have reached the end of pb_graph */
-    if (pb_type.num_modes == 0)
+    /* If pb_type is a primitive, we have reached the end of pb_graph */
+    if (pb_type.is_primitive())
         return (pb_type.depth);
 
     for (i = 0; i < pb_type.num_modes; ++i) {
@@ -221,30 +221,25 @@ static int draw_internal_find_max_lvl(const t_pb_type& pb_type) {
  * calls helper function to compute bounding box values.
  */
 static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height) {
-    int i, j, k;
-    t_pb_type* pb_type;
-    int num_modes, num_children, num_pb;
-    t_mode mode;
     float blk_width = 0.;
     float blk_height = 0.;
 
-    /* Get information about the pb_type */
-    pb_type = pb_graph_node->pb_type;
-    num_modes = pb_type->num_modes;
-
-    /* If no modes, we have reached the end of pb_graph */
-    if (num_modes == 0)
+    t_pb_type* pb_type = pb_graph_node->pb_type;
+    int num_modes = pb_type->num_modes;
+    /* If pb_type is primitive, we have reached the end of pb_graph */
+    if (pb_type->is_primitive()) {
         return;
+    }
 
-    for (i = 0; i < num_modes; ++i) {
-        mode = pb_type->modes[i];
-        num_children = mode.num_pb_type_children;
+    for (int i = 0; i < num_modes; ++i) {
+        t_mode mode = pb_type->modes[i];
+        int num_children = mode.num_pb_type_children;
 
-        for (j = 0; j < num_children; ++j) {
+        for (int j = 0; j < num_children; ++j) {
             /* Find the number of instances for each child pb_type. */
-            num_pb = mode.pb_type_children[j].num_pb;
+            int num_pb = mode.pb_type_children[j].num_pb;
 
-            for (k = 0; k < num_pb; ++k) {
+            for (int k = 0; k < num_pb; ++k) {
                 /* Compute bound box for block. Don't call if pb_type is root-level pb. */
                 draw_internal_calc_coords(type_descrip_index,
                                           &pb_graph_node->child_pb_graph_nodes[i][j][k],
@@ -721,7 +716,7 @@ t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const
     // and if pb is dud
     if (pb_type->depth + 1 > max_depth
         || pb->child_pbs == nullptr
-        || pb_type->num_modes == 0) {
+        || pb_type->is_primitive()) {
         return nullptr;
     }
 

vpr/src/pack/cluster_legalizer.cpp

@@ -65,7 +65,7 @@ static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set<AtomBlockId>&
     const AtomContext& atom_ctx = g_vpr_ctx.atom();
 
     const t_pb_type* pb_type = pb->pb_graph_node->pb_type;
-    if (pb_type->num_modes == 0) {
+    if (pb_type->is_primitive()) {
         /* primitive */
         AtomBlockId blk_id = atom_pb_lookup.pb_atom(pb);
         if (blk_id) {
@@ -396,7 +396,7 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_
 static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb, const AtomPBBimap& atom_to_pb) {
     const t_pb_type* cur_pb_type = cur_pb->pb_graph_node->pb_type;
 
-    VTR_ASSERT(cur_pb_type->num_modes == 0); /* primitive */
+    VTR_ASSERT(cur_pb_type->is_primitive()); /* primitive */
 
     AtomBlockId cur_pb_blk_id = atom_to_pb.pb_atom(cur_pb);
     if (cur_pb_blk_id && cur_pb_blk_id != blk_id) {
@@ -511,9 +511,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node,
         return e_block_pack_status::BLK_FAILED_FEASIBLE;
     }
 
-    bool is_primitive = (pb_type->num_modes == 0);
-
-    if (is_primitive) {
+    if (pb_type->is_primitive()) {
         VTR_ASSERT(!atom_to_pb.pb_atom(pb)
                    && atom_to_pb.atom_pb(blk_id) == nullptr
                    && atom_cluster[blk_id] == LegalizationClusterId::INVALID());
@@ -576,7 +574,7 @@ static void reset_lookahead_pins_used(t_pb* cur_pb) {
         return; /* No pins used, no need to continue */
     }
 
-    if (pb_type->num_modes > 0 && cur_pb->name != nullptr) {
+    if (!pb_type->is_primitive() && cur_pb->name != nullptr) {
         for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) {
             cur_pb->pb_stats->lookahead_input_pins_used[i].clear();
         }
@@ -821,7 +819,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb,
                                            const AtomPBBimap& atom_to_pb) {
     // run recursively till a leaf (primitive) pb block is reached
     const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type;
-    if (pb_type->num_modes > 0 && cur_pb->name != nullptr) {
+    if (!pb_type->is_primitive() && cur_pb->name != nullptr) {
         if (cur_pb->child_pbs != nullptr) {
             for (int i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; i++) {
                 if (cur_pb->child_pbs[i] != nullptr) {
@@ -835,6 +833,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb,
         // find if this child (primitive) pb block has an atom mapped to it,
         // if yes compute and mark lookahead pins used for that pb block
         AtomBlockId blk_id = atom_to_pb.pb_atom(cur_pb);
+        // TODO: Primitive pb_types should have non-null blif_model. Shoud this be an assertion?
         if (pb_type->blif_model != nullptr && blk_id) {
             compute_and_mark_lookahead_pins_used(blk_id, atom_cluster, atom_to_pb);
         }
@@ -848,7 +847,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb,
 static bool check_lookahead_pins_used(t_pb* cur_pb, t_ext_pin_util max_external_pin_util) {
     const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type;
 
-    if (pb_type->num_modes > 0 && cur_pb->name) {
+    if (!pb_type->is_primitive() && cur_pb->name) {
         for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) {
             size_t class_size = cur_pb->pb_graph_node->input_pin_class_size[i];
 
@@ -1015,7 +1014,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id,
 static void commit_lookahead_pins_used(t_pb* cur_pb) {
     const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type;
 
-    if (pb_type->num_modes > 0 && cur_pb->name) {
+    if (!pb_type->is_primitive() && cur_pb->name) {
         for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) {
             VTR_ASSERT(cur_pb->pb_stats->lookahead_input_pins_used[i].size() <= (unsigned int)cur_pb->pb_graph_node->input_pin_class_size[i]);
             for (size_t j = 0; j < cur_pb->pb_stats->lookahead_input_pins_used[i].size(); j++) {
@@ -1076,7 +1075,7 @@ static bool cleanup_pb(t_pb* pb) {
                     t_pb_type* pb_type = pb_child->pb_graph_node->pb_type;
 
                     /* Primitive, check occupancy */
-                    if (pb_type->num_modes == 0) {
+                    if (pb_type->is_primitive()) {
                         if (pb_child->name != nullptr) {
                             can_free = false;
                         }

vpr/src/pack/lb_type_rr_graph.cpp

@@ -296,7 +296,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n
     parent_node = pb_graph_node->parent_pb_graph_node;
     int num_modes;
 
-    if (pb_type->num_modes == 0) {
+    if (pb_type->is_primitive()) {
         /* This pb_graph_node is a terminating leaf node (primitive) */
 
         /* alloc and load input pins that connect to sinks */

vpr/src/pack/output_clustering.cpp

@@ -229,7 +229,7 @@ static std::string clustering_xml_interconnect_text(t_logical_block_type_ptr typ
     if (prev_node == OPEN) {
         /* No previous driver implies that this is either a top-level input pin or a primitive output pin */
         const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode);
-        VTR_ASSERT(cur_pin->parent_node->pb_type->parent_mode == nullptr || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT));
+        VTR_ASSERT(cur_pin->parent_node->pb_type->is_root() || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT));
         return clustering_xml_net_text(pb_route[inode].atom_net_id);
     } else {
         const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode);
@@ -330,7 +330,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo
                 for (j = 0; j < pb_type->ports[i].num_pins; j++) {
                     node_index = pb_graph_node->input_pins[port_index][j].pin_count_in_cluster;
 
-                    if (pb_type->parent_mode == nullptr) {
+                    if (pb_type->is_root()) {
                         pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
                     } else {
                         pins.push_back(clustering_xml_interconnect_text(type, pb_graph_pin_lookup_from_index_by_type, node_index, pb_route));
@@ -371,7 +371,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo
                 std::vector<std::string> pins;
                 for (j = 0; j < pb_type->ports[i].num_pins; j++) {
                     node_index = pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster;
-                    if (pb_type->parent_mode == nullptr) {
+                    if (pb_type->is_root()) {
                         pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
                     } else {
                         pins.push_back(clustering_xml_interconnect_text(type, pb_graph_pin_lookup_from_index_by_type, node_index, pb_route));
@@ -460,7 +460,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty
             for (j = 0; j < pb_type->ports[i].num_pins; j++) {
                 node_index = pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster;
 
-                if (pb_type->parent_mode == nullptr) {
+                if (pb_type->is_root()) {
                     if (pb_route.count(node_index)) {
                         pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
                     } else {
@@ -475,7 +475,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty
             //The cluster router may have rotated equivalent pins (e.g. LUT inputs),
             //record the resulting rotation here so it can be unambigously mapped
             //back to the atom netlist
-            if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->num_modes == 0) {
+            if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->is_primitive()) {
                 //This is a primitive with equivalent inputs
 
                 auto& atom_ctx = g_vpr_ctx.atom();
@@ -560,7 +560,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty
             std::vector<std::string> pins;
             for (j = 0; j < pb_type->ports[i].num_pins; j++) {
                 node_index = pb->pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster;
-                if (pb_type->parent_mode == nullptr) {
+                if (pb_type->is_root()) {
                     if (pb_route.count(node_index)) {
                         pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id));
                     } else {

vpr/src/pack/pb_type_graph.cpp

@@ -281,7 +281,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node,
     pb_graph_node->pin_num_range.low = pin_count_in_cluster;
     for (i = 0; i < pb_type->num_ports; i++) {
         if (pb_type->ports[i].model_port) {
-            VTR_ASSERT(pb_type->num_modes == 0);
+            VTR_ASSERT(pb_type->is_primitive());
         } else {
             VTR_ASSERT(pb_type->num_modes != 0 || pb_type->ports[i].is_clock);
         }

vpr/src/pack/pb_type_graph_annotations.cpp

@@ -47,7 +47,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
     pb_type = pb_graph_node->pb_type;
 
     /* Load primitive critical path delays */
-    if (pb_type->num_modes == 0) {
+    if (pb_type->is_primitive()) {
         annotations = pb_type->annotations;
         for (i = 0; i < pb_type->num_annotations; i++) {
             if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) {

vpr/src/pack/prepack.cpp

@@ -726,7 +726,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans
             // check if this input pin of the expansion edge has no driving pin
             if (expansion_edge->input_pins[i]->num_input_edges == 0) {
                 // check if this input pin of the expansion edge belongs to a root block (i.e doesn't have a parent block)
-                if (expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == nullptr) {
+                if (expansion_edge->input_pins[i]->parent_node->pb_type->is_root()) {
                     // This pack pattern extends to CLB (root pb block) input pin,
                     // thus it extends across multiple logic blocks, treat as a chain
                     packing_pattern.is_chain = true;

vpr/src/power/power_sizing.cpp

@@ -312,7 +312,7 @@ static double power_count_transistors_pb_node(t_pb_graph_node* pb_node) {
     t_pb_type* pb_type = pb_node->pb_type;
 
     /* Check if this is a leaf node, or whether it has children */
-    if (pb_type->num_modes == 0) {
+    if (pb_type->is_primitive()) {
         /* Leaf node */
         tc_interc_max = 0;
         tc_children_max = power_count_transistors_primitive(pb_type);

vpr/src/util/vpr_utils.cpp

@@ -708,7 +708,7 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg
 
     if (pb_type->blif_model != nullptr) {
         //Leaf pb_type
-        VTR_ASSERT(pb_type->num_modes == 0);
+        VTR_ASSERT(pb_type->is_primitive());
         if (std::regex_match(pb_type->blif_model, blif_model_regex)) {
             return true;
         } else {
@@ -769,7 +769,7 @@ int get_max_nets_in_pb_type(const t_pb_type* pb_type) {
             }
         }
     }
-    if (pb_type->parent_mode == nullptr) {
+    if (pb_type->is_root()) {
         max_nets += pb_type->num_input_pins + pb_type->num_output_pins
                     + pb_type->num_clock_pins;
     }
@@ -1169,7 +1169,7 @@ static void load_pin_id_to_pb_mapping_rec(t_pb* cur_pb, t_pb** pin_id_to_pb_mapp
         }
     }
 
-    if (pb_type->num_modes == 0 || cur_pb->child_pbs == nullptr) {
+    if (pb_type->is_primitive() || cur_pb->child_pbs == nullptr) {
         return;
     }