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Merge pull request #1968 from verilog-to-routing/remove-gridlocations-from-arch-tutorials
removed deprecated gridlocations xml tag from arch tutorials
2 parents fb75430 + e4f7bf2 commit d9719cf

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doc/src/tutorials/arch/classic_soft_logic.rst

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@@ -104,7 +104,6 @@ The ratio of tracks that a particular input/output pin of the CLB connects to is
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In this example, a fc_in of 0.15 means that each input pin connects to 15% of the available routing tracks in the external-to-CLB routing channel adjacent to that pin.
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The pinlocations tag is used to associate pins on the CLB with which side of the logic block pins reside on where the pattern spread corresponds to evenly spreading out the pins on all sides of the CLB in a round-robin fashion.
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In this example, the CLB has a total of 33 pins (22 input pins, 10 output pins, 1 clock pin) so 8 pins are assigned to all sides of the CLB except one side which gets assigned 9 pins.
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The columns occupied by complex blocks of type CLB is defined by gridlocations where fill means that all columns should be type CLB unless that column is taken up by a block with higher priority (where a larger number means a higher priority).
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.. code-block:: xml
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@@ -114,9 +113,7 @@ The columns occupied by complex blocks of type CLB is defined by gridlocations w
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<fc_out type="frac">0.125000</fc_out>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="fill" priority="1"/>
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</gridlocations>
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</pb_type>
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@@ -171,8 +168,6 @@ Classic Soft Logic Block Complete Example
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<fc_out type="frac">0.125000</fc_out>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="fill" priority="1"/>
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</gridlocations>
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</pb_type>
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doc/src/tutorials/arch/configurable_memory.rst

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@@ -258,14 +258,11 @@ A memory block with a reconfigurable aspect ratio.
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</interconnect>
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</mode>
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<fc_in type="frac"> 0.15</fc_in>
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<fc_out type="frac"> 0.125</fc_out>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="col" start="2" repeat="5" priority="2"/>
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</gridlocations>
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</pb_type>
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doc/src/tutorials/arch/configurable_memory_bus.rst

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@@ -138,7 +138,6 @@ A similar scheme is used at the outputs to ensure that either all outputs are re
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Finally, we model the relationship of the memory block with the general FPGA fabric.
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The ratio of tracks that a particular input/output pin of the CLB connects to is defined by fc_in/fc_out.
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The pinlocations describes which side of the logic block pins reside on where the pattern spread describes evenly spreading out the pins on all sides of the CLB in a round-robin fashion.
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The columns occupied by complex blocks of type CLB is defined by gridlocations where ``type="col" start="2" repeat="5"`` means that every fifth column starting from the second column type memory CLB unless that column is taken up by a block with higher priority (where a bigger number means a higher priority).
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.. code-block:: xml
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@@ -148,9 +147,6 @@ The columns occupied by complex blocks of type CLB is defined by gridlocations w
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<fc_out type="frac">0.125000</fc_out>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="col" start="2" repeat="5" priority="2"/>
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</gridlocations>
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@@ -248,6 +244,3 @@ Configurable Memory Bus-Based Complete Example
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<fc_out type="frac">0.125000</fc_out>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="col" start="2" repeat="5" priority="2"/>
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</gridlocations>

doc/src/tutorials/arch/fracturable_multiplier.rst

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@@ -166,15 +166,11 @@ A 36x36 multiplier fracturable into 18x18s and 9x9s
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</interconnect>
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</mode>
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<fc_in type="frac"> 0.15</fc_in>
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<fc_out type="frac"> 0.125</fc_out>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="col" start="4" repeat="5" priority="2"/>
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</gridlocations>
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</pb_type>
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doc/src/tutorials/arch/fracturable_multiplier_bus.rst

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@@ -373,8 +373,5 @@ Fracturable Multiplier Bus-Based Complete Example
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<loc side="right" offset="2">out[63:40]</loc>
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</pinlocations>
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<gridlocations>
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<loc type="col" start="4" repeat="5" priority="2"/>
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</gridlocations>
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</pb_type>
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