[Yosyslib]: - set extra memory address unconn instead of gnd, so VPR pack memory slices

	    - add a autoname stage in Yosys synthesis script to avoid VPR misinferring
	      the same signals as distinct ones
	    - perform dffunmap and opt fast as the last stages before wrtiing BLIF

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/misc/synthesis.ys

@@ -60,11 +60,6 @@ opt -full
 techmap 
 opt -fast
 
-flatten
-# Turn all DFFs into simple latches
-dffunmap
-opt -fast -noff
-
 # We read the definitions for all the VTR primitives
 # as blackboxes
 read_verilog -lib TTT/adder.v
@@ -79,14 +74,19 @@ read_verilog -lib DDD     #(DDD) will be replaced by dual_port_ram.v by python s
 read_verilog SSR         #(SSR) will be replaced by spram_rename.v by python script
 read_verilog DDR         #(DDR) will be replaced by dpram_rename.v by python script
 
-
+# Flatten the netlist
 flatten
+# Turn all DFFs into simple latches
+dffunmap
+opt -fast -noff
+
 # Lastly, check the hierarchy for any unknown modules,
 # and purge all modules (including blackboxes) that
 # aren't used
 hierarchy -check -purge_lib
 tee -o /dev/stdout stat
 
+autoname
 
 # Then write it out as a blif file, remembering to call
 # the internal `$true'/`$false' signals vcc/gnd, but

vtr_flow/misc/yosyslib/dual_port_ram.v

@@ -67,8 +67,8 @@ module dual_port_ram(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
                     .clk(clk), 
                     .we1(we1), 
                     .we2(we2), 
-                    .addr1(addr1), 
-                    .addr2(addr2), 
+                    .addr1({ {{`MEM_MAXADDR-ADDR_WIDTH}{1'bx}}, addr1[ADDR_WIDTH-1:0] }), 
+                    .addr2({ {{`MEM_MAXADDR-ADDR_WIDTH}{1'bx}}, addr2[ADDR_WIDTH-1:0] }), 
                     .data1(data1[i]), 
                     .data2(data2[i]), 
                     .out1(out1[i]),

vtr_flow/misc/yosyslib/single_port_ram.v

@@ -55,7 +55,7 @@ module single_port_ram(clk, we, addr, data, out);
                 singlePortRam uut (
                     .clk(clk), 
                     .we(we), 
-                    .addr(addr), 
+                    .addr({ {{`MEM_MAXADDR-ADDR_WIDTH}{1'bx}}, addr[ADDR_WIDTH-1:0] }), 
                     .data(data[i]), 
                     .out(out[i])
                 );