[Docs]: Fix a few typos and styles

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

doc/src/vtr/run_vtr_flow.rst

@@ -188,7 +188,7 @@ Detailed Command-line Options
 
 .. option:: -adder_cin_global
 
-    Tells ODIN II to connect the first cin in an adder/subtractorchain to a global gnd/vdd net.
+    Tells ODIN II to connect the first cin in an adder/subtractor chain to a global gnd/vdd net.
 
 .. option:: -use_odin_simulation 
 
@@ -208,34 +208,37 @@ Detailed Command-line Options
 
 .. option:: -elaborator <ELABORATOR>
 
-    Specify the elaborator of the synthesis flow for ODIN II [odin, yosys]
+    Specifies the elaborator of the synthesis flow for ODIN II [odin, yosys]
 
     **Default:** odin
 
 .. option:: -top_module <TOP_MODULE>
-                    Specify the name of the module in the design that should be considered as top
+    
+    Specifies the name of the module in the design that should be considered as top
 
 .. option:: -coarsen
 
-    Notify ODIN II if the input BLIF is coarse-grain
+    Notifies ODIN II if the input BLIF is coarse-grain
 
     **Default:** False
 
 .. option:: -fflegalize
 
-    Make flip-flops rising edge for coarse-grain input BLIFs in the techmap (ODIN II synthesis flow generates rising edge FFs by default, should be used for Yosys+Odin-II)
+    Makes flip-flops rising edge for coarse-grain input BLIFs in the techmap (ODIN II synthesis flow generates rising edge FFs by default, should be used for Yosys+Odin-II)
 
     **Default:** False
 
 .. option:: -encode_names
 
-    Enable Odin-II utilization of operation-type-encoded naming style for Yosys coarse-grained RTLIL nodes
+    Enables Odin-II utilization of operation-type-encoded naming style for Yosys coarse-grained RTLIL nodes
 
     **Default:** False
 
 .. option:: -yosys_script <YOSYS_SCRIPT>
 
-    Supplies Yosys with a .ys script file (similar to Tcl script), including synthesis steps. (default: None)
+    Supplies Yosys with a .ys script file (similar to Tcl script), including synthesis steps.
+    
+    **Default:** None
 
 .. option:: -parser <PARSER>
 
@@ -246,25 +249,25 @@ Detailed Command-line Options
 
 .. note::
 
-	The ``-parser`` option is only available for the Yosys standalone front-end.
+    The ``-parser`` option is only available for the Yosys standalone front-end.
     On the other hand, the Yosys+Odin-II front-end automatically determine the Yosys HDL parser according to the input file extension.
     If the input HDL type is not supported by the Yosys conventional Verilog front-end (i.e., ``read_verilog -sv``) and the Yosys plugins are not installed, the Yosys+Odin-II flow results in failure.
 
 
 .. code-block:: bash
 
-./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -elaborator yosys -fflegalize
-./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -elaborator yosys -fflegalize
-./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -elaborator yosys -fflegalize
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -elaborator yosys -fflegalize
+    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -elaborator yosys -fflegalize
+    ./run_vtr_flow <path/to/UHDM/File> <path/to/arch/file> -elaborator yosys -fflegalize
 
 Passes a Verilog/SystemVerilog/UHDM file to Yosys for performing elaboration. 
 The BLIF elaboration and partial mapping phases will be executed on the generated netlist by Odin-II, and all latches in the Yosys+Odin-II output file will be rising edge.
 Then ABC and VPR perform the default behaviour for the VTR flow, respectively.
 
 .. code-block:: bash
 
-./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -start yosys
-./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -start yosys
+    ./run_vtr_flow <path/to/Verilog/File> <path/to/arch/file> -start yosys
+    ./run_vtr_flow <path/to/SystemVerilog/File> <path/to/arch/file> -start yosys
 
 Running the VTR flow with the default behaviour using the Yosys standalone front-end.
 The parser for these runs is considered the Yosys conventional Verilog/SystemVerilog parser (i.e., ``read_verilog -sv``), as the parser is not explicitly specified.

doc/src/yosys+odin/dev_guide/contributing.rst

@@ -28,82 +28,82 @@ The flow is depicted in the figure below.
 
 .. code-block:: tcl
 
-	# FILE: $VTR_ROOT/ODIN_II/regression_test/tools/synth.tcl #
-	yosys -import
-
-	# the environment variable VTR_ROOT is set by Odin-II.
-	# Feel free to specify file paths using "$env(VTR_ROOT)/ ..." 
-	# Read VTR baseline library first
+    # FILE: $VTR_ROOT/ODIN_II/regression_test/tools/synth.tcl #
+    yosys -import
+    
+    # the environment variable VTR_ROOT is set by Odin-II.
+    # Feel free to specify file paths using "$env(VTR_ROOT)/ ..." 
+    # Read VTR baseline library first
     read_verilog -nomem2reg $env(ODIN_TECHLIB)/../../vtr_flow/primitives.v
     setattr -mod -set keep_hierarchy 1 single_port_ram
     setattr -mod -set keep_hierarchy 1 dual_port_ram
     
     # Read the HDL file with pre-defined parer in the "run_yosys.sh" script
     if {$env(PARSER) == "surelog" } {
-        puts "Using Yosys read_uhdm command"
-        plugin -i systemverilog;
-        yosys -import
-        read_uhdm -debug $env(TCL_CIRCUIT);
+    	puts "Using Yosys read_uhdm command"
+    	plugin -i systemverilog;
+    	yosys -import
+    	read_uhdm -debug $env(TCL_CIRCUIT);
     } elseif {$env(PARSER) == "yosys-plugin" } {
-        puts "Using Yosys read_systemverilog command"
-        plugin -i systemverilog;
-        yosys -import
-        read_systemverilog -debug $env(TCL_CIRCUIT)
+    	puts "Using Yosys read_systemverilog command"
+    	plugin -i systemverilog;
+    	yosys -import
+    	read_systemverilog -debug $env(TCL_CIRCUIT)
     } elseif {$env(PARSER) == "yosys" } {
-        puts "Using Yosys read_verilog command"
-        read_verilog -sv -nomem2reg -nolatches $env(TCL_CIRCUIT);
+    	puts "Using Yosys read_verilog command"
+    	read_verilog -sv -nomem2reg -nolatches $env(TCL_CIRCUIT);
     } else {
-        error "Invalid PARSER"
+    	error "Invalid PARSER"
     }
-
-	# Read the hardware decription Verilog
-	read_verilog -nomem2reg -nolatches PATH_TO_VERILOG_FILE.v;
-	# Check that cells match libraries and find top module
-	hierarchy -check -auto-top;
-
-	# Make name convention more readable
-	autoname;
-	# Translate processes to netlist components such as MUXs, FFs and latches
-	procs; opt;
-	# Extraction and optimization of finite state machines
-	fsm; opt;
-	# Collects memories, their port and create multiport memory cells
-	memory_collect; memory_dff; opt;
-
-	# Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
-	check;
-	# resolve asynchronous dffs
-	techmap -map $VTR_ROOT/ODIN_II/techlib/adff2dff.v;
-	techmap -map $VTR_ROOT/ODIN_II/techlib/adffe2dff.v;
+    
+    # Read the hardware decription Verilog
+    read_verilog -nomem2reg -nolatches PATH_TO_VERILOG_FILE.v;
+    # Check that cells match libraries and find top module
+    hierarchy -check -auto-top;
+    
+    # Make name convention more readable
+    autoname;
+    # Translate processes to netlist components such as MUXs, FFs and latches
+    procs; opt;
+    # Extraction and optimization of finite state machines
+    fsm; opt;
+    # Collects memories, their port and create multiport memory cells
+    memory_collect; memory_dff; opt;
+    
+    # Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
+    check;
+    # resolve asynchronous dffs
+    techmap -map $VTR_ROOT/ODIN_II/techlib/adff2dff.v;
+    techmap -map $VTR_ROOT/ODIN_II/techlib/adffe2dff.v;
     # To resolve Yosys internal indexed part-select circuitry
     techmap */t:\$shift */t:\$shiftx;
-
-	## Utilizing the "memory_bram" command and the Verilog design provided at "$VTR_ROOT/ODIN_II/techlib/mem_map.v"
-	## we could map Yosys memory blocks to BRAMs and ROMs before the Odin-II partial mapping phase.
-	## However, Yosys complains about expression widths more than 24 bits.
-	## E.g. reg [63:0] memory [18:0] ==> ERROR: Expression width 33554432 exceeds implementation limit of 16777216!
-	## Although we provided the required design files for this process (located in ODIN_II/techlib), we will handle
-	## memory blocks in the Odin-II BLIF elaborator and partial mapper. 
-	# memory_bram -rules $VTR_ROOT/ODIN_II/techlib/mem_rules.txt
-	# techmap -map $VTR_ROOT/ODIN_II/techlib/mem_map.v; 
-
-	# Transform the design into a new one with single top module
-	flatten;
-	# Transforms pmux into trees of regular multiplexers
-	pmuxtree;
+    
+    ## Utilizing the "memory_bram" command and the Verilog design provided at "$VTR_ROOT/ODIN_II/techlib/mem_map.v"
+    ## we could map Yosys memory blocks to BRAMs and ROMs before the Odin-II partial mapping phase.
+    ## However, Yosys complains about expression widths more than 24 bits.
+    ## E.g. reg [63:0] memory [18:0] ==> ERROR: Expression width 33554432 exceeds implementation limit of 16777216!
+    ## Although we provided the required design files for this process (located in ODIN_II/techlib), we will handle
+    ## memory blocks in the Odin-II BLIF elaborator and partial mapper. 
+    # memory_bram -rules $VTR_ROOT/ODIN_II/techlib/mem_rules.txt
+    # techmap -map $VTR_ROOT/ODIN_II/techlib/mem_map.v; 
+    
+    # Transform the design into a new one with single top module
+    flatten;
+    # Transforms pmux into trees of regular multiplexers
+    pmuxtree;
     # To possibly reduce words size
     wreduce;
-	# "undirven" to ensure there is no wire without drive
+    # "undirven" to ensure there is no wire without drive
     # "opt_muxtree" removes dead branches, "opt_expr" performs constant folding,
     # removes "undef" inputs from mux cells, and replaces muxes with buffers and inverters.
     # "-noff" a potential option to remove all sdff and etc. Only dff will remain
-	opt -undriven -full; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;
-	# Make name convention more readable
-	autoname;
-	# Print statistics
-	stat;
-	# Output BLIF
-	write_blif -param -impltf TCL_BLIF;
+    opt -undriven -full; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;
+    # Make name convention more readable
+    autoname;
+    # Print statistics
+    stat;
+    # Output BLIF
+    write_blif -param -impltf TCL_BLIF;
 
 **Algorithm 1** - The Yosys+Odin-II Tcl Script File
 

doc/src/yosys+odin/quickstart.rst

@@ -37,7 +37,7 @@ In this approach, the compile flag ``-DODIN_USE_YOSYS=ON`` should be passed to t
 
 .. note::
 
-	To take advantage of Yosys System Verilog and UHDM plugins, you need to pass the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` compile flag to CMake paramters.
+    Compiling the VTR flow with the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` flag is required to build and install Yosys SystemVerilog and UHDM plugins.
     Using this compile flag, the `Yosys-F4PGA-Plugins <https://github.com/chipsalliance/yosys-f4pga-plugins>`_ and `Surelog <https://github.com/chipsalliance/Surelog>`_ repositories are cloned in the ``$VTR_ROOT/libs/EXTERNAL`` directory and then will be compiled and added as external plugins to the Yosys front-end.
 
 .. note::

doc/src/yosys+odin/user_guide.rst

@@ -80,83 +80,82 @@ Example of Tcl script for Yosys+Odin-II
 
 .. code-block:: tcl
  
-	# FILE: $VTR_ROOT/ODIN_II/regression_test/tools/synth.tcl #
-	yosys -import
-
-	# the environment variable VTR_ROOT is set by Odin-II.
-
+    # FILE: $VTR_ROOT/ODIN_II/regression_test/tools/synth.tcl #
+    yosys -import
+    
+    # the environment variable VTR_ROOT is set by Odin-II.
+    
     # Read VTR baseline library first
     read_verilog -nomem2reg $env(ODIN_TECHLIB)/../../vtr_flow/primitives.v
     setattr -mod -set keep_hierarchy 1 single_port_ram
     setattr -mod -set keep_hierarchy 1 dual_port_ram
     
     # Read the HDL file with pre-defined parer in the "run_yosys.sh" script
     if {$env(PARSER) == "surelog" } {
-        puts "Using Yosys read_uhdm command"
-        plugin -i systemverilog;
-        yosys -import
-        read_uhdm -debug $env(TCL_CIRCUIT);
+    	puts "Using Yosys read_uhdm command"
+    	plugin -i systemverilog;
+    	yosys -import
+    	read_uhdm -debug $env(TCL_CIRCUIT);
     } elseif {$env(PARSER) == "yosys-plugin" } {
-        puts "Using Yosys read_systemverilog command"
-        plugin -i systemverilog;
-        yosys -import
-        read_systemverilog -debug $env(TCL_CIRCUIT)
+    	puts "Using Yosys read_systemverilog command"
+    	plugin -i systemverilog;
+    	yosys -import
+    	read_systemverilog -debug $env(TCL_CIRCUIT)
     } elseif {$env(PARSER) == "yosys" } {
-        puts "Using Yosys read_verilog command"
-        read_verilog -sv -nomem2reg -nolatches $env(TCL_CIRCUIT);
+    	puts "Using Yosys read_verilog command"
+    	read_verilog -sv -nomem2reg -nolatches $env(TCL_CIRCUIT);
     } else {
-        error "Invalid PARSER"
+    	error "Invalid PARSER"
     }
-
-	# Read the hardware decription Verilog
-	read_verilog -nomem2reg -nolatches PATH_TO_VERILOG_FILE.v;
-	# Check that cells match libraries and find top module
-	hierarchy -check -auto-top;
-
-	# Make name convention more readable
-	autoname;
-	# Translate processes to netlist components such as MUXs, FFs and latches
-	procs; opt;
-	# Extraction and optimization of finite state machines
-	fsm; opt;
-	# Collects memories, their port and create multiport memory cells
-	memory_collect; memory_dff; opt;
-
-	# Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
-	check;
-	# resolve asynchronous dffs
-	techmap -map $VTR_ROOT/ODIN_II/techlib/adff2dff.v;
-	techmap -map $VTR_ROOT/ODIN_II/techlib/adffe2dff.v;
+    
+    # Read the hardware decription Verilog
+    read_verilog -nomem2reg -nolatches PATH_TO_VERILOG_FILE.v;
+    # Check that cells match libraries and find top module
+    hierarchy -check -auto-top;
+    
+    # Make name convention more readable
+    autoname;
+    # Translate processes to netlist components such as MUXs, FFs and latches
+    procs; opt;
+    # Extraction and optimization of finite state machines
+    fsm; opt;
+    # Collects memories, their port and create multiport memory cells
+    memory_collect; memory_dff; opt;
+    
+    # Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
+    check;
+    # resolve asynchronous dffs
+    techmap -map $VTR_ROOT/ODIN_II/techlib/adff2dff.v;
+    techmap -map $VTR_ROOT/ODIN_II/techlib/adffe2dff.v;
     # To resolve Yosys internal indexed part-select circuitry
     techmap */t:\$shift */t:\$shiftx;
-
-	## Utilizing the "memory_bram" command and the Verilog design provided at "$VTR_ROOT/ODIN_II/techlib/mem_map.v"
-	## we could map Yosys memory blocks to BRAMs and ROMs before the Odin-II partial mapping phase.
-	## However, Yosys complains about expression widths more than 24 bits.
-	## E.g. reg [63:0] memory [18:0] ==> ERROR: Expression width 33554432 exceeds implementation limit of 16777216!
-	## Although we provided the required design files for this process (located in ODIN_II/techlib), we will handle
-	## memory blocks in the Odin-II BLIF elaborator and partial mapper. 
-	# memory_bram -rules $VTR_ROOT/ODIN_II/techlib/mem_rules.txt
-	# techmap -map $VTR_ROOT/ODIN_II/techlib/mem_map.v; 
-
-	# Transform the design into a new one with single top module
-	flatten;
-	# Transforms pmux into trees of regular multiplexers
-	pmuxtree;
+    
+    ## Utilizing the "memory_bram" command and the Verilog design provided at "$VTR_ROOT/ODIN_II/techlib/mem_map.v"
+    ## we could map Yosys memory blocks to BRAMs and ROMs before the Odin-II partial mapping phase.
+    ## However, Yosys complains about expression widths more than 24 bits.
+    ## E.g. reg [63:0] memory [18:0] ==> ERROR: Expression width 33554432 exceeds implementation limit of 16777216!
+    ## Although we provided the required design files for this process (located in ODIN_II/techlib), we will handle
+    ## memory blocks in the Odin-II BLIF elaborator and partial mapper. 
+    # memory_bram -rules $VTR_ROOT/ODIN_II/techlib/mem_rules.txt
+    # techmap -map $VTR_ROOT/ODIN_II/techlib/mem_map.v; 
+    
+    # Transform the design into a new one with single top module
+    flatten;
+    # Transforms pmux into trees of regular multiplexers
+    pmuxtree;
     # To possibly reduce words size
     wreduce;
-	# "undriven" to ensure there is no wire without drive
+    # "undriven" to ensure there is no wire without drive
     # "opt_muxtree" removes dead branches, "opt_expr" performs constant folding,
     # removes "undef" inputs from mux cells, and replaces muxes with buffers and inverters.
     # "-noff" a potential option to remove all sdff and etc. Only dff will remain
-	opt -undriven -full; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;
-	# Make name convention more readable
-	autoname;
-	# Print statistics
-	stat;
-	# Output BLIF
-	write_blif -param -impltf TCL_BLIF;
-
+    opt -undriven -full; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;
+    # Make name convention more readable
+    autoname;
+    # Print statistics
+    stat;
+    # Output BLIF
+    write_blif -param -impltf TCL_BLIF;
 
 .. note::
 

doc/src/yosys/quickstart.rst

@@ -34,7 +34,7 @@ The compile flag ``-DWITH_YOSYS=ON`` should be passed to the CMake parameters to
 
 .. note::
 
-	Compiling the VTR flow with the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` flag is required to build and install Yosys SystemVerilog and UHDM plugins.
+    Compiling the VTR flow with the ``-DYOSYS_SV_UHDM_PLUGIN=ON`` flag is required to build and install Yosys SystemVerilog and UHDM plugins.
     Using this compile flag, the `Yosys-F4PGA-Plugins <https://github.com/chipsalliance/yosys-f4pga-plugins>`_ and `Surelog <https://github.com/chipsalliance/Surelog>`_ repositories are cloned in the ``$VTR_ROOT/libs/EXTERNAL`` directory and then will be compiled and added as external plugins to the Yosys front-end.