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acomodikmurray
acomodi
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clock aliases: add check through all clock aliases when getting clocks
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent b39e968 commit d6d2767

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5 files changed

+136
-9
lines changed

5 files changed

+136
-9
lines changed

‎vpr/src/timing/read_sdc.cpp

Lines changed: 25 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,7 @@ class SdcParseCallback : public sdcparse::Callback {
162162

163163
AtomNetId clock_net = netlist_.pin_net(*netlist_clock_drivers_.begin());
164164
std::string clock_name = netlist_.net_name(clock_net);
165+
165166
domain = tc_.find_clock_domain(clock_name);
166167
} else {
167168
vpr_throw(VPR_ERROR_SDC, fname_.c_str(), lineno_,
@@ -911,18 +912,33 @@ class SdcParseCallback : public sdcparse::Callback {
911912

912913
bool found = false;
913914
for (tatum::DomainId domain : tc_.clock_domains()) {
914-
const std::string& clock_name = tc_.clock_domain_name(domain);
915-
if (std::regex_match(clock_name, clock_regex)) {
916-
found = true;
915+
const auto& clock_name = tc_.clock_domain_name(domain);
916+
917+
if (tc_.is_virtual_clock(domain)) {
918+
if (std::regex_match(clock_name, clock_regex)) {
919+
found = true;
920+
921+
domains.insert(domain);
922+
}
923+
} else {
924+
auto net_aliases = netlist_.net_aliases(clock_name);
925+
926+
for (const auto& alias : net_aliases) {
927+
if (std::regex_match(alias, clock_regex)) {
928+
found = true;
917929

918-
domains.insert(domain);
930+
domains.insert(domain);
931+
// Exit the inner loop as the net is already being constrained
932+
break;
933+
}
934+
}
919935
}
920-
}
921936

922-
if (!found) {
923-
VTR_LOGF_WARN(fname_.c_str(), lineno_,
924-
"get_clocks target name or pattern '%s' matched no clocks\n",
925-
clock_glob_pattern.c_str());
937+
if (!found) {
938+
VTR_LOGF_WARN(fname_.c_str(), lineno_,
939+
"get_clocks target name or pattern '%s' matched no clocks\n",
940+
clock_glob_pattern.c_str());
941+
}
926942
}
927943
}
928944

‎vtr_flow/benchmarks/blif/clock_set_delay_aliases.blif

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
# Generated by Yosys 0.9+2406 (git sha1 4d685890, clang 6.0.0-1ubuntu2 -fPIC -Os)
2+
3+
.model top
4+
.inputs clk1 clk2
5+
.outputs led[0] led[1]
6+
.names $false
7+
.names $true
8+
1
9+
.names $undef
10+
.names counter_1.count[0] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.X[0]
11+
0 1
12+
.names counter_1.count[1] counter_1.count[0] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[1]
13+
10 1
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01 1
15+
.names counter_1.count[1] counter_1.count[0] $abc$300$new_n19_
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0- 1
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-0 1
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.names $abc$300$new_n19_ counter_1.count[2] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[2]
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11 1
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00 1
21+
.names counter_1.count[2] $abc$300$new_n19_ $abc$300$new_n21_
22+
10 1
23+
.names $abc$300$new_n21_ counter_1.count[3] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[3]
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10 1
25+
01 1
26+
.names counter_2.count[0] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.X[0]
27+
0 1
28+
.names counter_2.count[1] counter_2.count[0] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[1]
29+
10 1
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01 1
31+
.names counter_2.count[1] counter_2.count[0] $abc$300$new_n25_
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0- 1
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-0 1
34+
.names $abc$300$new_n25_ counter_2.count[2] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[2]
35+
11 1
36+
00 1
37+
.names counter_2.count[2] $abc$300$new_n25_ $abc$300$new_n27_
38+
10 1
39+
.names $abc$300$new_n27_ counter_2.count[3] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[3]
40+
10 1
41+
01 1
42+
.latch $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.X[0] counter_1.count[0] re clk1 0
43+
.latch $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[1] counter_1.count[1] re clk1 0
44+
.latch $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[2] counter_1.count[2] re clk1 0
45+
.latch $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[3] counter_1.count[3] re clk1 0
46+
.latch $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.X[0] counter_2.count[0] re clk2 0
47+
.latch $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[1] counter_2.count[1] re clk2 0
48+
.latch $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[2] counter_2.count[2] re clk2 0
49+
.latch $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[3] counter_2.count[3] re clk2 0
50+
.names counter_1.count[1] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.X[1]
51+
1 1
52+
.names counter_1.count[2] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.X[2]
53+
1 1
54+
.names counter_1.count[3] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.X[3]
55+
1 1
56+
.names $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.X[0] $flatten\counter_1.$auto$alumacc.cc:485:replace_alu$5.Y[0]
57+
1 1
58+
.names counter_2.count[1] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.X[1]
59+
1 1
60+
.names counter_2.count[2] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.X[2]
61+
1 1
62+
.names counter_2.count[3] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.X[3]
63+
1 1
64+
.names $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.X[0] $flatten\counter_2.$auto$alumacc.cc:485:replace_alu$5.Y[0]
65+
1 1
66+
.names clk1 counter_1.clk_counter
67+
1 1
68+
.names counter_1.count[3] counter_1.out
69+
1 1
70+
.names clk2 counter_2.clk_counter
71+
1 1
72+
.names counter_2.count[3] counter_2.out
73+
1 1
74+
.names counter_1.count[3] led[0]
75+
1 1
76+
.names counter_2.count[3] led[1]
77+
1 1
78+
.end

‎vtr_flow/sdc/samples/clock_aliases/set_delay.sdc

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
create_clock -period 10.0 counter_1.clk_counter
2+
create_clock -period 5.0 counter_2.clk_counter
3+
4+
set_max_delay 40 -from [get_clocks {counter_1.clk_counter}] -to [get_clocks {counter_2.clk_counter}]

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/config.txt

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
#
2+
############################################
3+
# Configuration file for running experiments
4+
##############################################
5+
6+
# Path to directory of circuits to use
7+
circuits_dir=benchmarks/blif
8+
9+
# Path to directory of architectures to use
10+
archs_dir=arch
11+
12+
# Add circuits to list to sweep
13+
circuit_list_add=clock_set_delay_aliases.blif
14+
15+
# Add architectures to list to sweep
16+
arch_list_add=timing/k6_N10_40nm.xml
17+
18+
# Parse info and how to parse
19+
parse_file=vpr_standard.txt
20+
21+
# How to parse QoR info
22+
qor_parse_file=qor_standard.txt
23+
24+
# Pass requirements
25+
pass_requirements_file=pass_requirements.txt
26+
27+
script_params_common =-starting_stage vpr --absorb_buffer_luts on
28+
script_params_list_add = -sdc_file sdc/samples/clock_aliases/set_delay.sdc

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ regression_tests/vtr_reg_strong/strong_clock_buf
6060
regression_tests/vtr_reg_strong/strong_equivalent_sites
6161
regression_tests/vtr_reg_strong/strong_absorb_buffers
6262
regression_tests/vtr_reg_strong/strong_clock_aliases
63+
regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay
6364
regression_tests/vtr_reg_strong/strong_graphics_commands
6465
regression_tests/vtr_reg_strong/strong_clock_pll
6566
regression_tests/vtr_reg_strong/strong_place_effort_scaling

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