equivalent: added bimap to store pin mappings between tile and block

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/physical_types.h

@@ -38,6 +38,7 @@
 
 #include "vtr_ndmatrix.h"
 #include "vtr_hash.h"
+#include "vtr_bimap.h"
 
 #include "logic_types.h"
 #include "clock_types.h"
@@ -58,6 +59,8 @@ struct t_physical_tile_type;
 typedef const t_physical_tile_type* t_physical_tile_type_ptr;
 struct t_logical_block_type;
 typedef const t_logical_block_type* t_logical_block_type_ptr;
+struct t_logical_pin;
+struct t_physical_pin;
 struct t_pb_type;
 struct t_pb_graph_pin_power;
 struct t_mode;
@@ -616,12 +619,44 @@ struct t_physical_tile_type {
 
     /* Unordered map indexed by the logical block index.
      * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */
-    std::unordered_map<int, std::unordered_map<int, int>> tile_block_pin_directs_map;
+    std::unordered_map<int, vtr::bimap<t_logical_pin, t_physical_pin>> tile_block_pin_directs_map;
 
     /* Returns the indices of pins that contain a clock for this physical logic block */
     std::vector<int> get_clock_pins_indices() const;
 };
 
+struct t_logical_pin {
+    int pin = -1;
+
+    t_logical_pin(int value) {
+        pin = value;
+    }
+
+    bool operator==(const t_logical_pin o) const {
+        return pin == o.pin;
+    }
+
+    bool operator<(const t_logical_pin o) const {
+        return pin < o.pin;
+    }
+};
+
+struct t_physical_pin {
+    int pin = -1;
+
+    t_physical_pin(int value) {
+        pin = value;
+    }
+
+    bool operator==(const t_physical_pin o) const {
+        return pin == o.pin;
+    }
+
+    bool operator<(const t_physical_pin o) const {
+        return pin < o.pin;
+    }
+};
+
 /** Describes I/O and clock ports of a physical tile type
  *
  *  It corresponds to <port/> tags in the FPGA architecture description

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -52,6 +52,7 @@
 #include "vtr_memory.h"
 #include "vtr_digest.h"
 #include "vtr_token.h"
+#include "vtr_bimap.h"
 
 #include "arch_types.h"
 #include "arch_util.h"
@@ -3251,7 +3252,7 @@ static void ProcessEquivalentSiteDirects(pugi::xml_node Parent,
                        "There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), PhysicalTileType->name);
     }
 
-    std::unordered_map<int, int> directs_map;
+    vtr::bimap<t_logical_pin, t_physical_pin> directs_map;
 
     CurDirect = Parent.first_child();
     while (CurDirect) {
@@ -3279,7 +3280,16 @@ static void ProcessEquivalentSiteDirects(pugi::xml_node Parent,
 
         int num_pins = from_pins.second - from_pins.first;
         for (int i = 0; i < num_pins; i++) {
-            directs_map[to_pins.first + i] = from_pins.first + i;
+            t_physical_pin phy_pin(from_pins.first + i);
+            t_logical_pin log_pin(to_pins.first + i);
+
+            auto result = directs_map.insert(log_pin, phy_pin);
+            if (!result.second) {
+                archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
+                               "Duplicate logical pin (%d) to physical pin (%d) mappings found for "
+                               "Physical Tile %s and Logical Block %s.\n",
+                               log_pin.pin, phy_pin.pin, PhysicalTileType->name, LogicalBlockType->name);
+            }
         }
 
         CurDirect = CurDirect.next_sibling(CurDirect.name());
@@ -4791,6 +4801,42 @@ static void link_physical_logical_types(std::vector<t_physical_tile_type>& Physi
             archfpga_throw(__FILE__, __LINE__,
                            "Logical Block %s does not have any equivalent tiles.\n", logical_block.name);
         }
+
+        std::unordered_map<int, bool> ignored_pins_check_map;
+        std::unordered_map<int, bool> global_pins_check_map;
+
+        for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) {
+            for (auto& tile : logical_block.equivalent_tiles) {
+                auto direct_map = tile->tile_block_pin_directs_map.at(logical_block.index);
+                auto result = direct_map.find(t_logical_pin(pin));
+                if (result == direct_map.end()) {
+                    archfpga_throw(__FILE__, __LINE__,
+                                   "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n",
+                                   pin, tile->name, logical_block.name);
+                }
+
+                int phy_index = result->second.pin;
+
+                bool is_ignored = tile->is_ignored_pin[phy_index];
+                bool is_global = tile->is_pin_global[phy_index];
+
+                auto ignored_result = ignored_pins_check_map.insert(std::pair<int, bool>(pin, is_ignored));
+                if (!ignored_result.second && ignored_result.first->second != is_ignored) {
+                    archfpga_throw(__FILE__, __LINE__,
+                                   "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) "
+                                   "different from the corresponding pins of the other equivalent sites\n.",
+                                   tile->name, phy_index, pin);
+                }
+
+                auto global_result = global_pins_check_map.insert(std::pair<int, bool>(pin, is_global));
+                if (!global_result.second && global_result.first->second != is_global) {
+                    archfpga_throw(__FILE__, __LINE__,
+                                   "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) "
+                                   "different from the corresponding pins of the other equivalent sites\n.",
+                                   tile->name, phy_index, pin);
+                }
+            }
+        }
     }
 }
 
@@ -4812,8 +4858,8 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t
     }
 
     for (auto pin_map : pin_direct_mapping) {
-        auto block_port = get_port_by_pin(logical_block, pin_map.first);
-        auto tile_port = get_port_by_pin(physical_tile, pin_map.second);
+        auto block_port = get_port_by_pin(logical_block, pin_map.first.pin);
+        auto tile_port = get_port_by_pin(physical_tile, pin_map.second.pin);
 
         VTR_ASSERT(block_port != nullptr);
         VTR_ASSERT(tile_port != nullptr);

vpr/src/route/route_common.cpp

@@ -1033,11 +1033,9 @@ static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t
             node_block_pin = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
 
             auto pin_directs_map = type->tile_block_pin_directs_map;
-            auto map_result = pin_directs_map.find(logical_block->index);
-            std::unordered_map<int, int> map = map_result->second;
+            auto map = pin_directs_map[logical_block->index];
 
-            auto pin_result = map.find(node_block_pin);
-            auto orig_phys_pin = pin_result->second;
+            auto orig_phys_pin = map[t_logical_pin(node_block_pin)].pin;
 
             VTR_ASSERT(type->num_pins % type->capacity == 0);
             int max_num_block_pins = type->num_pins / type->capacity;