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| 1 | +/** |
| 2 | + * Copyright (c) 2021 Seyed Alireza Damghani ([email protected]) |
| 3 | + * |
| 4 | + * Permission is hereby granted, free of charge, to any person |
| 5 | + * obtaining a copy of this software and associated documentation |
| 6 | + * files (the "Software"), to deal in the Software without |
| 7 | + * restriction, including without limitation the rights to use, |
| 8 | + * copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 9 | + * copies of the Software, and to permit persons to whom the |
| 10 | + * Software is furnished to do so, subject to the following |
| 11 | + * conditions: |
| 12 | + * |
| 13 | + * The above copyright notice and this permission notice shall be |
| 14 | + * included in all copies or substantial portions of the Software. |
| 15 | + * |
| 16 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 17 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 18 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 20 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 21 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 23 | + * OTHER DEALINGS IN THE SOFTWARE. |
| 24 | + * |
| 25 | + * @file: includes the definition of VERILOG Writer class to write a |
| 26 | + * given netlist in a Verilog file. In addition to the netlist, the |
| 27 | + * target architecture hardblocks(DSPs) can be outputed as a blackbox. |
| 28 | + * With that said, only the DSPs' declaration are printed. |
| 29 | + */ |
| 30 | + |
| 31 | +#include <sstream> //std::stringstream |
| 32 | + |
| 33 | +#include "Verilog.hpp" |
| 34 | +#include "odin_globals.h" |
| 35 | +#include "hard_blocks.h" |
| 36 | +#include "vtr_util.cpp" |
| 37 | + |
| 38 | +Verilog::Writer::Writer() |
| 39 | + : GenericWriter() { |
| 40 | + this->models_declaration = sc_new_string_cache(); |
| 41 | + } |
| 42 | + |
| 43 | +Verilog::Writer::~Writer() = default; |
| 44 | + |
| 45 | +inline void Verilog::Writer::_create_file(const char* file_name, const file_type_e file_type) { |
| 46 | + // validate the file_name pointer |
| 47 | + oassert(file_name); |
| 48 | + // validate the file type |
| 49 | + if (file_type != _VERILOG) |
| 50 | + error_message(UTIL, unknown_location, |
| 51 | + "Verilog back-end entity cannot create file types(%d) other than Verilog", file_type); |
| 52 | + // create the Verilog file and set it as the output file |
| 53 | + this->output_file = create_verilog(file_name); |
| 54 | +} |
| 55 | + |
| 56 | + |
| 57 | +void Verilog::Writer::_write(const netlist_t* netlist) { |
| 58 | + |
| 59 | + // to write the top module and netlist components |
| 60 | + if (netlist) { |
| 61 | + /* [TODO] */ |
| 62 | + } |
| 63 | + |
| 64 | + // print out the rest od models, including DSPs in the target architecture |
| 65 | + t_model* model = Arch.models; |
| 66 | + |
| 67 | + while(model) { |
| 68 | + int sc_spot; |
| 69 | + if ((sc_spot = sc_lookup_string(this->models_declaration, model->name)) != -1){ |
| 70 | + fprintf(this->output_file, "%s", (char*)this->models_declaration->data[sc_spot]); |
| 71 | + fflush(this->output_file); |
| 72 | + } |
| 73 | + model = model->next; |
| 74 | + } |
| 75 | +} |
| 76 | + |
| 77 | +/** |
| 78 | + *------------------------------------------------------------------------------------------- |
| 79 | + * (function: create_verilog) |
| 80 | + * |
| 81 | + * @brief initiate a new output file stream |
| 82 | + * |
| 83 | + * @param file_name the path to the verilog file |
| 84 | + * |
| 85 | + * @return an output stream to the verilog file |
| 86 | + *------------------------------------------------------------------------------------------- |
| 87 | + */ |
| 88 | +FILE* Verilog::Writer::create_verilog(const char* file_name) { |
| 89 | + FILE* out = NULL; |
| 90 | + |
| 91 | + /* open the file for output */ |
| 92 | + out = fopen(file_name, "w"); |
| 93 | + |
| 94 | + if (out == NULL) { |
| 95 | + error_message(UTIL, unknown_location, "Could not open output file %s\n", file_name); |
| 96 | + } |
| 97 | + return (out); |
| 98 | +} |
| 99 | + |
| 100 | + |
| 101 | +/** |
| 102 | + *------------------------------------------------------------------------------------------- |
| 103 | + * (function: declare_blackbox) |
| 104 | + * |
| 105 | + * @brief find the corresponding blackbox with the given |
| 106 | + * name in the given target arhitecture, then add its |
| 107 | + * Verilog declartion to this->models_declaration string cache. |
| 108 | + * |
| 109 | + * @param bb_name the blackbox(DSP) name |
| 110 | + * |
| 111 | + * @return a long value, which is representing the index of |
| 112 | + * the declartion in models string cache. Will return -1 if |
| 113 | + * a DSP with the given name does not exist in the architecture. |
| 114 | + *------------------------------------------------------------------------------------------- |
| 115 | + */ |
| 116 | +long Verilog::Writer::declare_blackbox(const char* bb_name) { |
| 117 | + /* to validate the blackbox name */ |
| 118 | + oassert(bb_name); |
| 119 | + |
| 120 | + t_model* bb = find_hard_block(bb_name); |
| 121 | + if (bb == NULL) { |
| 122 | + error_message(UTIL, unknown_location, |
| 123 | + "Odin-II failed to find DSP module \"%s\" in the target device.", bb_name); |
| 124 | + } |
| 125 | + |
| 126 | + std::stringstream bb_declaration; |
| 127 | + |
| 128 | + // need to specify "(* blackbox *)" tag if Yosys |
| 129 | + // is going to elaborate the Verilog file |
| 130 | + if (elaborator_e::_YOSYS) { |
| 131 | + bb_declaration << BLACKBOX_ATTR << NEWLINE; |
| 132 | + } |
| 133 | + |
| 134 | + bb_declaration << MODULE << TAB << bb_name << OPEN_PARENTHESIS << std::endl; |
| 135 | + bb_declaration << declare_ports(bb) << std::endl; |
| 136 | + bb_declaration << CLOSE_PARENTHESIS << SEMICOLON << std::endl; |
| 137 | + bb_declaration << HARD_BLOCK_COMMENT << std::endl; |
| 138 | + bb_declaration << END_MODULE << NEWLINE << std::endl; |
| 139 | + |
| 140 | + int sc_spot; |
| 141 | + if ((sc_spot = sc_add_string(this->models_declaration, bb->name)) != -1 ) { |
| 142 | + this->models_declaration->data[sc_spot] = (void*) vtr::strdup(bb_declaration.str().c_str()); |
| 143 | + return (sc_spot); |
| 144 | + } |
| 145 | + |
| 146 | + return (-1); |
| 147 | +} |
| 148 | + |
| 149 | +/** |
| 150 | + *------------------------------------------------------------------------------------------- |
| 151 | + * (function: declare_ports) |
| 152 | + * |
| 153 | + * @brief generate a string that includes the declaration |
| 154 | + * of input/output ports of a given t_model |
| 155 | + * |
| 156 | + * @param model the DSP t_model pointer |
| 157 | + * |
| 158 | + * @return a string value including the declaration of all |
| 159 | + * input/output ports related to the given DSP model |
| 160 | + *------------------------------------------------------------------------------------------- |
| 161 | + */ |
| 162 | +std::string Verilog::Writer::declare_ports(t_model* model) { |
| 163 | + /* to validate the model pointer */ |
| 164 | + oassert(model); |
| 165 | + |
| 166 | + std::stringstream input_stream; |
| 167 | + t_model_ports* input_port = model->inputs; |
| 168 | + while(input_port) { |
| 169 | + input_stream << TAB |
| 170 | + << INPUT_PORT << TAB |
| 171 | + << OPEN_SQUARE_BRACKET |
| 172 | + << input_port->size << COLON << "0" |
| 173 | + << CLOSE_SQUARE_BRACKET |
| 174 | + << TAB << input_port->name |
| 175 | + << COMMA << std::endl; |
| 176 | + |
| 177 | + // move forward until the end of input ports' list |
| 178 | + input_port = input_port->next; |
| 179 | + } |
| 180 | + |
| 181 | + std::stringstream output_stream; |
| 182 | + t_model_ports* output_port = model->outputs; |
| 183 | + while(output_port) { |
| 184 | + output_stream << TAB |
| 185 | + << OUTPUT_PORT << TAB |
| 186 | + << OPEN_SQUARE_BRACKET |
| 187 | + << output_port->size << COLON << "0" |
| 188 | + << CLOSE_SQUARE_BRACKET |
| 189 | + << TAB << output_port->name |
| 190 | + << COMMA << std::endl; |
| 191 | + |
| 192 | + // move forward until the end of output ports' list |
| 193 | + output_port = output_port->next; |
| 194 | + } |
| 195 | + |
| 196 | + std::string input_str = input_stream.str(); |
| 197 | + std::string output_str = output_stream.str(); |
| 198 | + |
| 199 | + // check the value of input/output ports declaration |
| 200 | + // to trim extra last semicolon if required |
| 201 | + std::stringstream ports_declaration; |
| 202 | + if (!input_stream.str().empty() && output_stream.str().empty()) { |
| 203 | + input_str[input_str.find_last_not_of(COMMA)-1] = '\0'; |
| 204 | + ports_declaration << input_str; |
| 205 | + } else if (!output_stream.str().empty()) { |
| 206 | + if (!input_stream.str().empty()) |
| 207 | + ports_declaration << input_str; |
| 208 | + |
| 209 | + ports_declaration << output_str.substr(0, output_str.find_last_not_of(COMMA)-1); |
| 210 | + } |
| 211 | + |
| 212 | + // return the string value |
| 213 | + return (ports_declaration.str()); |
| 214 | +} |
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