Allowed clock to be routable (still needs fixing)

Author: mustafabbas

libs/libarchfpga/src/physical_types.h

@@ -434,7 +434,8 @@ constexpr int DEFAULT_SWITCH = -2;
  * pin_avg_width_offset: Average width offset to specified pin (exact if only a single physical pin instance)
  * pin_avg_height_offset: Average height offset to specified pin (exact if only a single physical pin instance)
  * pin_class: The class a pin belongs to
- * is_global_pin: Whether or not a pin is global (hence not routed)
+ * is_global_pin: Whether or not a pin is global
+ * is_routed_pin: Wether or not nets connected to this pin are routed
  *
  * fc_specs: The Fc specifications for all pins
  *
@@ -476,6 +477,7 @@ struct t_type_descriptor /* TODO rename this.  maybe physical type descriptor or
     std::vector<int> pin_height_offset; //[0..num_pins-1]
 	int *pin_class = nullptr; /* [0..num_pins-1] */
 	bool *is_global_pin = nullptr; /* [0..num_pins-1] */
+    std::vector<bool> is_routed_pin; // [0..num_pins -1]
 
     std::vector<t_fc_specification> fc_specs;
 

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -527,9 +527,11 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations,
 	Type->num_class = num_class;
 	Type->pin_class = (int*) vtr::malloc(Type->num_pins * sizeof(int) * capacity);
 	Type->is_global_pin = (bool*) vtr::malloc( Type->num_pins * sizeof(bool)* capacity);
+    Type->is_routed_pin.resize(Type->num_pins * sizeof(bool)* capacity);
 	for (i = 0; i < Type->num_pins * capacity; i++) {
 		Type->pin_class[i] = OPEN;
 		Type->is_global_pin[i] = true;
+        Type->is_routed_pin[i] = true;
 	}
 
 	pin_count = 0;
@@ -563,6 +565,8 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations,
 				Type->pin_class[pin_count] = num_class;
 				Type->is_global_pin[pin_count] = Type->pb_type->ports[j].is_clock ||
                     Type->pb_type->ports[j].is_non_clock_global;
+                Type->is_routed_pin[pin_count] = !Type->pb_type->ports[j].is_clock &&
+                    !Type->pb_type->ports[j].is_non_clock_global;
 				pin_count++;
 
 				if (Type->pb_type->ports[j].equivalent == PortEquivalence::NONE) {

vpr/src/base/SetupVPR.cpp

@@ -207,6 +207,10 @@ void SetupVPR(t_options *Options,
         ClockModeling::treat_clock_pins_as_non_globals();
     }
 
+    if (Options->clock_modeling == DEDICATED_NETWORK) {
+        ClockModeling::assign_clock_pins_as_routable();
+    }
+
     if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_LB_TYPE_RR_GRAPH)) {
 		echo_lb_type_rr_graphs(getEchoFileName(E_ECHO_LB_TYPE_RR_GRAPH),*PackerRRGraphs);
 	}

vpr/src/base/clock_modeling.cpp

@@ -8,14 +8,37 @@ void ClockModeling::treat_clock_pins_as_non_globals() {
 
     for (int type_idx = 0; type_idx < device_ctx.num_block_types; type_idx++) {
 
-        auto type = device_ctx.block_types[type_idx];
-        if(type.pb_type) {
-            for(auto clock_pin_idx : type.get_clock_pins_indices()) {
+        auto* type = &(device_ctx.block_types[type_idx]);
+        if(type->pb_type) {
+            for(auto clock_pin_idx : type->get_clock_pins_indices()) {
 
                // clock pins should be originally considered as global when reading the architecture
-               VTR_ASSERT(type.is_global_pin[clock_pin_idx]);
+               VTR_ASSERT(type->is_global_pin[clock_pin_idx]);
+               VTR_ASSERT(!type->is_routed_pin[clock_pin_idx]);
 
-               type.is_global_pin[clock_pin_idx] = false;
+               type->is_global_pin[clock_pin_idx] = false;
+               type->is_routed_pin[clock_pin_idx] = true;
+            }
+        }
+    }
+}
+
+void ClockModeling::assign_clock_pins_as_routable() {
+
+    auto& device_ctx = g_vpr_ctx.device();
+
+    for (int type_idx = 0; type_idx < device_ctx.num_block_types; type_idx++) {
+
+        auto* type = &(device_ctx.block_types[type_idx]);
+        if(type->pb_type) {
+            for(auto clock_pin_idx : type->get_clock_pins_indices()) {
+
+               // clock pins are gloabl pins
+               // however should have been orignally assigned as unroutable
+               VTR_ASSERT(type->is_global_pin[clock_pin_idx]);
+               VTR_ASSERT(!type->is_routed_pin[clock_pin_idx]);
+
+               //type->is_routed_pin[clock_pin_idx] = true;
             }
         }
     }

vpr/src/base/clock_modeling.h

@@ -10,10 +10,15 @@ enum e_clock_modeling {
 
 namespace ClockModeling
 {
-    /* Removes global pin flag from clock pins.
+    /* Removes global pin flag from clock pins and adds routable pin flag for clock pins
        This causes clock nets to also be treated as non-global;
        therefore, they will be routed using inter-block routing */
     void treat_clock_pins_as_non_globals();
+
+    /* Sets the is_routable_pin flag for clock pins. This allows for clock nets to be routed
+       Note: this does not remove the global pin flag from clocks (therefore rr_graph generation
+       in rr_graph.cpp is not effected by this change) */
+    void assign_clock_pins_as_routable();
 }
 
 #endif

vpr/src/base/read_netlist.cpp

@@ -945,8 +945,11 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
 					VTR_ASSERT(j == clb_nlist.pin_physical_index(*(clb_nlist.net_pins(clb_net_id).begin() + count[clb_net_id])));
 					VTR_ASSERT(j == clb_nlist.net_pin_physical_index(clb_net_id, count[clb_net_id]));
 
-					if (clb_nlist.block_type(blk_id)->is_global_pin[j])
+                    // Sets nets that connect to non routed pins to be global nets (i.e. not routed)
+					if (!clb_nlist.block_type(blk_id)->is_routed_pin[j]) {
+                        VTR_ASSERT(clb_nlist.block_type(blk_id)->is_global_pin[j]);
 						clb_nlist.set_net_is_global(clb_net_id, true);
+                    }
                     /* Error check performed later to ensure no mixing of global and non-global signals */
 
 				} else {

vpr/src/route/route_timing.cpp

@@ -36,6 +36,9 @@
 
 #define CONGESTED_SLOPE_VAL -0.04
 
+//Print out extensive debug information about router operations
+//#define ROUTER_DEBUG
+
 constexpr float CONGESTED_ITERATION_THRESHOLD_FACTOR = 0.8;
 
 enum class RouterCongestionMode {