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Allowed clock to be routable (still needs fixing)
1 parent 1a8e7f3 commit d2f23bb

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7 files changed

+52
-8
lines changed

7 files changed

+52
-8
lines changed

libs/libarchfpga/src/physical_types.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -434,7 +434,8 @@ constexpr int DEFAULT_SWITCH = -2;
434434
* pin_avg_width_offset: Average width offset to specified pin (exact if only a single physical pin instance)
435435
* pin_avg_height_offset: Average height offset to specified pin (exact if only a single physical pin instance)
436436
* pin_class: The class a pin belongs to
437-
* is_global_pin: Whether or not a pin is global (hence not routed)
437+
* is_global_pin: Whether or not a pin is global
438+
* is_routed_pin: Wether or not nets connected to this pin are routed
438439
*
439440
* fc_specs: The Fc specifications for all pins
440441
*
@@ -476,6 +477,7 @@ struct t_type_descriptor /* TODO rename this. maybe physical type descriptor or
476477
std::vector<int> pin_height_offset; //[0..num_pins-1]
477478
int *pin_class = nullptr; /* [0..num_pins-1] */
478479
bool *is_global_pin = nullptr; /* [0..num_pins-1] */
480+
std::vector<bool> is_routed_pin; // [0..num_pins -1]
479481

480482
std::vector<t_fc_specification> fc_specs;
481483

libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -527,9 +527,11 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations,
527527
Type->num_class = num_class;
528528
Type->pin_class = (int*) vtr::malloc(Type->num_pins * sizeof(int) * capacity);
529529
Type->is_global_pin = (bool*) vtr::malloc( Type->num_pins * sizeof(bool)* capacity);
530+
Type->is_routed_pin.resize(Type->num_pins * sizeof(bool)* capacity);
530531
for (i = 0; i < Type->num_pins * capacity; i++) {
531532
Type->pin_class[i] = OPEN;
532533
Type->is_global_pin[i] = true;
534+
Type->is_routed_pin[i] = true;
533535
}
534536

535537
pin_count = 0;
@@ -563,6 +565,8 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations,
563565
Type->pin_class[pin_count] = num_class;
564566
Type->is_global_pin[pin_count] = Type->pb_type->ports[j].is_clock ||
565567
Type->pb_type->ports[j].is_non_clock_global;
568+
Type->is_routed_pin[pin_count] = !Type->pb_type->ports[j].is_clock &&
569+
!Type->pb_type->ports[j].is_non_clock_global;
566570
pin_count++;
567571

568572
if (Type->pb_type->ports[j].equivalent == PortEquivalence::NONE) {

vpr/src/base/SetupVPR.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,10 @@ void SetupVPR(t_options *Options,
207207
ClockModeling::treat_clock_pins_as_non_globals();
208208
}
209209

210+
if (Options->clock_modeling == DEDICATED_NETWORK) {
211+
ClockModeling::assign_clock_pins_as_routable();
212+
}
213+
210214
if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_LB_TYPE_RR_GRAPH)) {
211215
echo_lb_type_rr_graphs(getEchoFileName(E_ECHO_LB_TYPE_RR_GRAPH),*PackerRRGraphs);
212216
}

vpr/src/base/clock_modeling.cpp

Lines changed: 28 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,37 @@ void ClockModeling::treat_clock_pins_as_non_globals() {
88

99
for (int type_idx = 0; type_idx < device_ctx.num_block_types; type_idx++) {
1010

11-
auto type = device_ctx.block_types[type_idx];
12-
if(type.pb_type) {
13-
for(auto clock_pin_idx : type.get_clock_pins_indices()) {
11+
auto* type = &(device_ctx.block_types[type_idx]);
12+
if(type->pb_type) {
13+
for(auto clock_pin_idx : type->get_clock_pins_indices()) {
1414

1515
// clock pins should be originally considered as global when reading the architecture
16-
VTR_ASSERT(type.is_global_pin[clock_pin_idx]);
16+
VTR_ASSERT(type->is_global_pin[clock_pin_idx]);
17+
VTR_ASSERT(!type->is_routed_pin[clock_pin_idx]);
1718

18-
type.is_global_pin[clock_pin_idx] = false;
19+
type->is_global_pin[clock_pin_idx] = false;
20+
type->is_routed_pin[clock_pin_idx] = true;
21+
}
22+
}
23+
}
24+
}
25+
26+
void ClockModeling::assign_clock_pins_as_routable() {
27+
28+
auto& device_ctx = g_vpr_ctx.device();
29+
30+
for (int type_idx = 0; type_idx < device_ctx.num_block_types; type_idx++) {
31+
32+
auto* type = &(device_ctx.block_types[type_idx]);
33+
if(type->pb_type) {
34+
for(auto clock_pin_idx : type->get_clock_pins_indices()) {
35+
36+
// clock pins are gloabl pins
37+
// however should have been orignally assigned as unroutable
38+
VTR_ASSERT(type->is_global_pin[clock_pin_idx]);
39+
VTR_ASSERT(!type->is_routed_pin[clock_pin_idx]);
40+
41+
//type->is_routed_pin[clock_pin_idx] = true;
1942
}
2043
}
2144
}

vpr/src/base/clock_modeling.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,15 @@ enum e_clock_modeling {
1010

1111
namespace ClockModeling
1212
{
13-
/* Removes global pin flag from clock pins.
13+
/* Removes global pin flag from clock pins and adds routable pin flag for clock pins
1414
This causes clock nets to also be treated as non-global;
1515
therefore, they will be routed using inter-block routing */
1616
void treat_clock_pins_as_non_globals();
17+
18+
/* Sets the is_routable_pin flag for clock pins. This allows for clock nets to be routed
19+
Note: this does not remove the global pin flag from clocks (therefore rr_graph generation
20+
in rr_graph.cpp is not effected by this change) */
21+
void assign_clock_pins_as_routable();
1722
}
1823

1924
#endif

vpr/src/base/read_netlist.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -945,8 +945,11 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
945945
VTR_ASSERT(j == clb_nlist.pin_physical_index(*(clb_nlist.net_pins(clb_net_id).begin() + count[clb_net_id])));
946946
VTR_ASSERT(j == clb_nlist.net_pin_physical_index(clb_net_id, count[clb_net_id]));
947947

948-
if (clb_nlist.block_type(blk_id)->is_global_pin[j])
948+
// Sets nets that connect to non routed pins to be global nets (i.e. not routed)
949+
if (!clb_nlist.block_type(blk_id)->is_routed_pin[j]) {
950+
VTR_ASSERT(clb_nlist.block_type(blk_id)->is_global_pin[j]);
949951
clb_nlist.set_net_is_global(clb_net_id, true);
952+
}
950953
/* Error check performed later to ensure no mixing of global and non-global signals */
951954

952955
} else {

vpr/src/route/route_timing.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@
3636

3737
#define CONGESTED_SLOPE_VAL -0.04
3838

39+
//Print out extensive debug information about router operations
40+
//#define ROUTER_DEBUG
41+
3942
constexpr float CONGESTED_ITERATION_THRESHOLD_FACTOR = 0.8;
4043

4144
enum class RouterCongestionMode {

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