second round of updating the base code to be consistent with .clang-format file

Author: soheilshahrouz

libs/libarchfpga/src/device_grid.h

@@ -19,7 +19,6 @@ struct t_grid_tile {
     const t_metadata_dict* meta = nullptr;
 };
 
-
 //TODO: All of the functions that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually.
 /**
  * @class DeviceGrid

libs/libarchfpga/src/physical_types.h

@@ -703,8 +703,6 @@ struct t_physical_tile_type {
      * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */
     std::unordered_map<int, std::unordered_map<int, vtr::bimap<t_logical_pin, t_physical_pin>>> tile_block_pin_directs_map;
 
-
-
     // TODO: Remove is_input_type / is_output_type as part of
     // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193
 
@@ -714,7 +712,7 @@ struct t_physical_tile_type {
     // Does this t_physical_tile_type contain an outpad?
     bool is_output_type = false;
 
-  public:   // Function members
+  public: // Function members
     ///@brief Returns the indices of pins that contain a clock for this physical logic block
     std::vector<int> get_clock_pins_indices() const;
 
@@ -1280,8 +1278,8 @@ struct t_pin_to_pin_annotation {
  *      flat_site_index       : Index of this primitive site within its primitive type within this cluster type.
  *                              Values are in [0...total_primitive_count-1], e.g. if there are 10 ALMs per cluster, 2 FFS
  *                              and 2 LUTs per ALM, then flat site indices for FFs would run from 0 to 19, and flat site
-                                indices for LUTs would run from 0 to 19. This member is only used by nodes corresponding
-                                to primitive sites. It is used when reconstructing clusters from a flat placement file.
+ * indices for LUTs would run from 0 to 19. This member is only used by nodes corresponding
+ * to primitive sites. It is used when reconstructing clusters from a flat placement file.
  *      illegal_modes         : vector containing illegal modes that result in conflicts during routing
  */
 class t_pb_graph_node {
@@ -1335,7 +1333,7 @@ class t_pb_graph_node {
 
     int total_pb_pins; /* only valid for top-level */
 
-    void* temp_scratch_pad;                                     /* temporary data, useful for keeping track of things when traversing data structure */
+    void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */
 
     int* input_pin_class_size;  /* Stores the number of pins that belong to a particular input pin class */
     int num_input_pin_class;    /* number of input pin classes that this pb_graph_node has */
@@ -1345,7 +1343,6 @@ class t_pb_graph_node {
     int total_primitive_count; /* total number of this primitive type in the cluster */
     int flat_site_index;       /* index of this primitive within sites of its type in this cluster  */
 
-
     /* Interconnect instances for this pb
      * Only used for power
      */
@@ -1988,7 +1985,7 @@ struct t_switchblock_inf {
     /* We can also define a region to apply this SB to all locations falls into this region using regular expression in the architecture file*/
     t_sb_loc_spec reg_x;
     t_sb_loc_spec reg_y;
-    
+
     t_permutation_map permutation_map; /* map holding the permutation functions attributed to this switchblock */
 
     std::vector<t_wireconn_inf> wireconns; /* list of wire types/groups this SB will connect */
@@ -2145,11 +2142,11 @@ struct t_arch {
     std::vector<std::string> ipin_cblock_switch_name;
 
     std::vector<t_grid_def> grid_layouts; //Set of potential device layouts
-    
+
     //the layout that is chosen to be used with command line options
     //It is used to generate custom SB for a specific locations within the device
     //If the layout is not specified in the command line options, this variable will be set to "auto"
-    std::string device_layout; 
+    std::string device_layout;
 
     t_clock_arch_spec clock_arch; // Clock related data types
 

libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp

@@ -18,8 +18,8 @@
  * @param noc_ref To be filled with NoC router locations and their connectivity.
  */
 static void process_topology(pugi::xml_node topology_tag,
-                            const pugiutil::loc_data& loc_data,
-                            t_noc_inf* noc_ref);
+                             const pugiutil::loc_data& loc_data,
+                             t_noc_inf* noc_ref);
 
 /**
  * @brief Process a <router> tag under a <topology> tag.
@@ -50,8 +50,8 @@ static void process_router(pugi::xml_node router_tag,
  * @param noc_ref To be filled with NoC router locations and their connectivity.
  */
 static void process_mesh_topology(pugi::xml_node mesh_topology_tag,
-                                  const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref);
-
+                                  const pugiutil::loc_data& loc_data,
+                                  t_noc_inf* noc_ref);
 
 /**
  * Create routers and set their properties so that a mesh grid of routers is created.
@@ -69,9 +69,12 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag,
 static void generate_noc_mesh(pugi::xml_node mesh_topology_tag,
                               const pugiutil::loc_data& loc_data,
                               t_noc_inf* noc_ref,
-                              float mesh_region_start_x, float mesh_region_end_x,
-                              float mesh_region_start_y, float mesh_region_end_y,
-                              int mesh_region_start_layer, int mesh_region_end_layer,
+                              float mesh_region_start_x,
+                              float mesh_region_end_x,
+                              float mesh_region_start_y,
+                              float mesh_region_end_y,
+                              int mesh_region_start_layer,
+                              int mesh_region_end_layer,
                               int mesh_size);
 
 /**
@@ -153,7 +156,6 @@ void process_noc_tag(pugi::xml_node noc_tag,
 
     const std::vector<std::string> expected_noc_children_tags = {"mesh", "topology"};
 
-
     // identifier that lets us know when we could not properly convert a string conversion value
     std::string attribute_conversion_failure_string;
 
@@ -270,9 +272,12 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag,
 static void generate_noc_mesh(pugi::xml_node mesh_topology_tag,
                               const pugiutil::loc_data& loc_data,
                               t_noc_inf* noc_ref,
-                              float mesh_region_start_x, float mesh_region_end_x,
-                              float mesh_region_start_y, float mesh_region_end_y,
-                              int mesh_region_start_layer, int mesh_region_end_layer,
+                              float mesh_region_start_x,
+                              float mesh_region_end_x,
+                              float mesh_region_start_y,
+                              float mesh_region_end_y,
+                              int mesh_region_start_layer,
+                              int mesh_region_end_layer,
                               int mesh_size) {
     // check that the mesh size of the router is not 0
     if (mesh_size == 0) {
@@ -306,8 +311,7 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag,
     float horizontal_router_separation = (mesh_region_end_x - mesh_region_start_x) / (mesh_size - 1);
 
     // improper region check
-    if (vertical_router_separation <= 0 || horizontal_router_separation <= 0 ||
-        mesh_region_end_layer < mesh_region_start_layer) {
+    if (vertical_router_separation <= 0 || horizontal_router_separation <= 0 || mesh_region_end_layer < mesh_region_start_layer) {
         archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag),
                        "The NoC region is invalid.");
     }
@@ -378,8 +382,8 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag,
  * Go through each router in the NoC and store the list of routers that connect to it.
  */
 static void process_topology(pugi::xml_node topology_tag,
-                            const pugiutil::loc_data& loc_data,
-                            t_noc_inf* noc_ref) {
+                             const pugiutil::loc_data& loc_data,
+                             t_noc_inf* noc_ref) {
     // The topology tag should have no attributes, check that
     pugiutil::expect_only_attributes(topology_tag, {}, loc_data);
 
@@ -652,8 +656,7 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag,
             }
 
             auto it = std::find_if(noc_ref.router_list.begin(), noc_ref.router_list.end(), [src, dst](const t_router& router) {
-                return router.id == src &&
-                       std::find(router.connection_list.begin(), router.connection_list.end(), dst) != router.connection_list.end();
+                return router.id == src && std::find(router.connection_list.begin(), router.connection_list.end(), dst) != router.connection_list.end();
             });
 
             if (it == noc_ref.router_list.end()) {
@@ -667,14 +670,14 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag,
                 double latency = std::atof(link_latency_override);
                 if (latency <= 0.0) {
                     archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag),
-                                   "The override link latency value for link (%d, %d) must be positive:%g." ,
+                                   "The override link latency value for link (%d, %d) must be positive:%g.",
                                    src, dst, latency);
                 }
 
                 auto [_, success] = noc_ref.link_latency_overrides.insert({{src, dst}, latency});
                 if (!success) {
                     archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag),
-                                   "The latency for link (%d, %d) was overridden once before." ,
+                                   "The latency for link (%d, %d) was overridden once before.",
                                    src, dst);
                 }
             }
@@ -684,14 +687,14 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag,
                 double bandwidth = std::atof(link_latency_override);
                 if (bandwidth <= 0.0) {
                     archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag),
-                                   "The override link bandwidth value for link (%d, %d) must be positive:%g." ,
+                                   "The override link bandwidth value for link (%d, %d) must be positive:%g.",
                                    src, dst, bandwidth);
                 }
 
                 auto [_, success] = noc_ref.link_bandwidth_overrides.insert({{src, dst}, bandwidth});
                 if (!success) {
                     archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag),
-                                   "The bandwidth for link (%d, %d) was overridden once before." ,
+                                   "The bandwidth for link (%d, %d) was overridden once before.",
                                    src, dst);
                 }
             }

vpr/src/analytical_place/analytical_solver.cpp

@@ -265,7 +265,7 @@ static inline void update_linear_system_with_anchors(Eigen::SparseMatrix<double>
                                                      PartialPlacement& p_placement,
                                                      size_t num_moveable_blocks,
                                                      vtr::vector<APRowId, APBlockId> row_id_to_blk_id,
-                                                        unsigned iteration) {
+                                                     unsigned iteration) {
     // Anchor weights grow exponentially with iteration.
     double coeff_pseudo_anchor = 0.01 * std::exp((double)iteration / 5);
     for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks; row_id_idx++) {

vpr/src/analytical_place/detailed_placer.cpp

@@ -23,42 +23,40 @@
 #include "vpr_types.h"
 #include "vpr_utils.h"
 
-std::unique_ptr<DetailedPlacer> make_detailed_placer(
-                        e_ap_detailed_placer detailed_placer_type,
-                        const BlkLocRegistry& curr_clustered_placement,
-                        const AtomNetlist& atom_netlist,
-                        const ClusteredNetlist& clustered_netlist,
-                        t_vpr_setup& vpr_setup,
-                        const t_arch& arch) {
+std::unique_ptr<DetailedPlacer> make_detailed_placer(e_ap_detailed_placer detailed_placer_type,
+                                                     const BlkLocRegistry& curr_clustered_placement,
+                                                     const AtomNetlist& atom_netlist,
+                                                     const ClusteredNetlist& clustered_netlist,
+                                                     t_vpr_setup& vpr_setup,
+                                                     const t_arch& arch) {
     switch (detailed_placer_type) {
         case e_ap_detailed_placer::Identity:
             return std::make_unique<IdentityDetailedPlacer>();
         case e_ap_detailed_placer::Annealer:
-            return std::make_unique<AnnealerDetailedPlacer>(
-                                                        curr_clustered_placement,
-                                                        atom_netlist,
-                                                        clustered_netlist,
-                                                        vpr_setup,
-                                                        arch);
+            return std::make_unique<AnnealerDetailedPlacer>(curr_clustered_placement,
+                                                            atom_netlist,
+                                                            clustered_netlist,
+                                                            vpr_setup,
+                                                            arch);
         default:
             VPR_FATAL_ERROR(VPR_ERROR_AP,
                             "Unrecognized detailed placer type");
     }
 }
 
-AnnealerDetailedPlacer::AnnealerDetailedPlacer(
-                                const BlkLocRegistry& curr_clustered_placement,
-                                const AtomNetlist& atom_netlist,
-                                const ClusteredNetlist& clustered_netlist,
-                                t_vpr_setup& vpr_setup,
-                                const t_arch& arch)
-            : DetailedPlacer(),
-              // TODO: These two variables needed to be stored in the class since
-              //       the Placer stores a reference to these objects. These
-              //       should really be initialized and stored into the Placer
-              //       class directly.
-              pb_gpin_lookup_(g_vpr_ctx.device().logical_block_types),
-              netlist_pin_lookup_(clustered_netlist, atom_netlist, pb_gpin_lookup_) {
+AnnealerDetailedPlacer::AnnealerDetailedPlacer(const BlkLocRegistry& curr_clustered_placement,
+                                               const AtomNetlist& atom_netlist,
+                                               const ClusteredNetlist& clustered_netlist,
+                                               t_vpr_setup& vpr_setup,
+                                               const t_arch& arch)
+    : DetailedPlacer(
+    ,
+    // TODO: These two variables needed to be stored in the class since
+    //       the Placer stores a reference to these objects. These
+    //       should really be initialized and stored into the Placer
+    //       class directly.
+    pb_gpin_lookup_(g_vpr_ctx.device().logical_block_types)
+    , netlist_pin_lookup_(clustered_netlist, atom_netlist, pb_gpin_lookup_) {
     // Initialize the place delay model.
     // TODO: This initialization is complicated. Should be moved within create_delay_model
     //       or something.
@@ -106,4 +104,3 @@ void AnnealerDetailedPlacer::optimize_placement() {
     // clusters.
     post_place_sync();
 }
-

vpr/src/analytical_place/detailed_placer.h

@@ -22,7 +22,7 @@
  * flow).
  */
 class DetailedPlacer {
-public:
+  public:
     virtual ~DetailedPlacer() {}
 
     DetailedPlacer() = default;
@@ -36,14 +36,12 @@ class DetailedPlacer {
 /**
  * @brief A factory method which creates a Detailed Placer of the given type.
  */
-std::unique_ptr<DetailedPlacer> make_detailed_placer(
-                        e_ap_detailed_placer detailed_placer_type,
-                        const BlkLocRegistry& curr_clustered_placement,
-                        const AtomNetlist& atom_netlist,
-                        const ClusteredNetlist& clustered_netlist,
-                        t_vpr_setup& vpr_setup,
-                        const t_arch& arch);
-
+std::unique_ptr<DetailedPlacer> make_detailed_placer(e_ap_detailed_placer detailed_placer_type,
+                                                     const BlkLocRegistry& curr_clustered_placement,
+                                                     const AtomNetlist& atom_netlist,
+                                                     const ClusteredNetlist& clustered_netlist,
+                                                     t_vpr_setup& vpr_setup,
+                                                     const t_arch& arch);
 
 /**
  * @brief The Identity Detailed Placer.
@@ -53,7 +51,7 @@ std::unique_ptr<DetailedPlacer> make_detailed_placer(
  * with.
  */
 class IdentityDetailedPlacer : public DetailedPlacer {
-public:
+  public:
     using DetailedPlacer::DetailedPlacer;
 
     void optimize_placement() final {}
@@ -71,7 +69,7 @@ class IdentityDetailedPlacer : public DetailedPlacer {
  * stage. So options passed to the Placer will be used in here.
  */
 class AnnealerDetailedPlacer : public DetailedPlacer {
-public:
+  public:
     /**
      * @brief Construct the Annealer Detailed Placer class.
      *
@@ -98,7 +96,7 @@ class AnnealerDetailedPlacer : public DetailedPlacer {
      */
     void optimize_placement() final;
 
-private:
+  private:
     /// @brief The placer class, which contains the annealer.
     std::unique_ptr<Placer> placer_;
 
@@ -108,4 +106,3 @@ class AnnealerDetailedPlacer : public DetailedPlacer {
     /// @brief A lookup between CLB pins and atom pins.
     ClusteredPinAtomPinsLookup netlist_pin_lookup_;
 };
-

vpr/src/analytical_place/flat_placement_bins.h

@@ -42,7 +42,7 @@ typedef vtr::StrongId<flat_placement_bin_tag, size_t> FlatPlacementBinId;
  * higher level classes.
  */
 class FlatPlacementBins {
-public:
+  public:
     // Iterator for the flat placement bin IDs
     typedef typename vtr::vector_map<FlatPlacementBinId, FlatPlacementBinId>::const_iterator bin_iterator;
 
@@ -110,7 +110,8 @@ class FlatPlacementBins {
      */
     inline const vtr::Rect<double>& bin_region(FlatPlacementBinId bin_id) const {
         VTR_ASSERT(bin_id.is_valid());
-        return bin_region_[bin_id];;
+        return bin_region_[bin_id];
+        ;
     }
 
     /**
@@ -179,7 +180,7 @@ class FlatPlacementBins {
         return true;
     }
 
-private:
+  private:
     /// @brief A vector of the Flat Placement Bin IDs. If any of them are invalid,
     ///        then that means that the bin has been destroyed.
     vtr::vector_map<FlatPlacementBinId, FlatPlacementBinId> bin_ids_;
@@ -194,4 +195,3 @@ class FlatPlacementBins {
     // TODO: For 3D FPGAs, this should be a 3D rectangle.
     vtr::vector_map<FlatPlacementBinId, vtr::Rect<double>> bin_region_;
 };
-