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[Yosys+Odin-II]: replace Yosys RTLIL subcircuit names with their output pin name,
(should be unique for each subcircuit) to enhance the readability and ease of CP tracking in VTR final timing analysis Signed-off-by: Seyed Alireza Damghani <[email protected]>
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+22
-10
lines changed

1 file changed

+22
-10
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ODIN_II/SRC/BLIFReader.cpp

Lines changed: 22 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -336,10 +336,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
336336
t_model* hb_model = NULL;
337337
nnode_t* new_node = allocate_nnode(my_location);
338338

339-
// Name the node subcircuit_name~hard_block_number so that the name is unique.
340339
static long hard_block_number = 0;
341-
odin_sprintf(buffer, "%s~%ld", subcircuit_name, hard_block_number++);
342-
new_node->name = make_full_ref_name(buffer, NULL, NULL, NULL, -1);
343340

344341
// init the edge sensitivity of hard block
345342
if (configuration.coarsen)
@@ -357,21 +354,15 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
357354
new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
358355

359356
if (new_node->type == NO_OP) {
360-
char new_name[READ_BLIF_BUFFER];
361-
vtr::free(new_node->name);
362357
/* in case of weird names, need to add memories manually */
363358
int sc_spot = -1;
364359
char* yosys_subckt_str = NULL;
365360
if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
366361
/* specify node type */
367362
new_node->type = yosys_subckt_strmap[yosys_subckt_str];
368-
/* specify node name */
369-
odin_sprintf(new_name, "\\%s~%ld", yosys_subckt_str, hard_block_number - 1);
370363
} else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
371364
/* specify node type */
372365
new_node->type = HARD_IP;
373-
/* specify node name */
374-
odin_sprintf(new_name, "\\%s~%ld", subcircuit_stripped_name, hard_block_number - 1);
375366
/* Detect used hard block for the blif generation */
376367
hb_model = find_hard_block(subcircuit_stripped_name);
377368
if (hb_model) {
@@ -381,7 +372,6 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
381372
error_message(PARSE_BLIF, unknown_location,
382373
"Unsupported subcircuit type (%s) in BLIF file.\n", subcircuit_name);
383374
}
384-
new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
385375

386376
// CLEAN UP
387377
vtr::free(yosys_subckt_str);
@@ -493,6 +483,28 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
493483
output_nets_hash->add(name, new_net);
494484
}
495485

486+
if (!configuration.coarsen || new_node->type == SPRAM || new_node->type == DPRAM) {
487+
// Name the node subcircuit_name~hard_block_number so that the name is unique.
488+
odin_sprintf(buffer, "%s~%ld", subcircuit_name, hard_block_number++);
489+
new_node->name = make_full_ref_name(buffer, NULL, NULL, NULL, -1);
490+
} else {
491+
// Find the basename of the output pin and name the node
492+
// with BASENAME^TYPE
493+
char* splitter = strrchr(new_node->output_pins[0]->net->name, '.');
494+
char* output_pin_fullname = new_node->output_pins[0]->net->name;
495+
496+
// there is only a top module, no instantiation of submodules
497+
if (splitter == NULL)
498+
splitter = strchr(output_pin_fullname, '^');
499+
500+
char basename[READ_BLIF_BUFFER];
501+
size_t basename_len = splitter - output_pin_fullname;
502+
503+
strncpy(basename, output_pin_fullname, basename_len);
504+
basename[basename_len] = '\0';
505+
new_node->name = node_name(new_node, basename);
506+
}
507+
496508
// Create a fake ast node.
497509
if (!configuration.coarsen || new_node->type == HARD_IP) {
498510
new_node->related_ast_node = create_node_w_type(HARD_BLOCK, my_location);

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