heterogeneous: added sub tile strong reg test golden results

acomodi · acomodi · commit cf0d77bfc63f · 2020-04-02T13:52:46.000+02:00
Signed-off-by: Alessandro Comodi &lt;acomodi@antmicro.com&gt;
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/config.txt
@@ -24,5 +24,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 # Script parameters
-#script_params=""
-script_params = -track_memory_usage -lut_size 1 -starting_stage vpr
+script_params=-track_memory_usage -lut_size 1 -starting_stage vpr
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt
@@ -0,0 +1,2 @@
+arch         	circuit       	script_params	vtr_flow_elapsed_time	error	odin_synth_time	max_odin_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_revision                    	vpr_status	hostname	rundir                                                                                                                        	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_time	placed_wirelength_est	place_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	crit_path_route_time
+sub_tiles.xml	sub_tiles.blif	common       	2.58                 	     	-1             	-1          	-1       	-1            	-1          	-1          	-1         	-1      	-1         	-1     	1     	-1          	-1      	v8.0.0-rc2-1568-g7a7333ca8-dirty	success   	acomodi 	/data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run015/sub_tiles.xml/sub_tiles.blif/common	38400      	1                 	1                  	3                  	4                    	0                 	3                   	4                     	3           	3            	9                	-1                       	auto       	0.00     	6                    	2.22      	3.85145       	-3.85145            	-3.85145            	1             	3                	2                                     	14813.4               	29626.8              	-1                               	-1                                  	0.01                     	3                          	2                                	4                          	4                                 	432                        	283                      	3.85145            	-3.85145 	-3.85145 	0       	0       	-1                          	-1                             	0.00                

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	+arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
	`2`	+sub_tiles.xml sub_tiles.blif common 2.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc2-1568-g7a7333ca8-dirty success acomodi /data/vtr-symbiflow/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run015/sub_tiles.xml/sub_tiles.blif/common 38400 1 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 2.22 3.85145 -3.85145 -3.85145 1 3 2 14813.4 29626.8 -1 -1 0.01 3 2 4 4 432 283 3.85145 -3.85145 -3.85145 0 0 -1 -1 0.00