@@ -105,8 +105,10 @@ static vtr::NdMatrix<std::vector<int>, 5> alloc_and_load_pin_to_track_map(const
105
105
const int * sets_per_seg_type);
106
106
107
107
static vtr::NdMatrix<int , 6 > alloc_and_load_pin_to_seg_type (const e_pin_type pin_type,
108
+ const vtr::Matrix<int >& Fc,
108
109
const int seg_type_tracks,
109
- const int Fc,
110
+ const int seg_index,
111
+ const int max_Fc,
110
112
const t_physical_tile_type_ptr Type,
111
113
const std::set<int > type_layer,
112
114
const bool perturb_switch_pattern,
@@ -283,9 +285,10 @@ static void alloc_and_load_tile_rr_graph(RRGraphBuilder& rr_graph_builder,
283
285
static float pattern_fmod (float a, float b);
284
286
static void load_uniform_connection_block_pattern (vtr::NdMatrix<int , 6 >& tracks_connected_to_pin,
285
287
const std::vector<t_pin_loc>& pin_locations,
288
+ const vtr::Matrix<int >& Fc,
289
+ const int seg_index,
286
290
const int x_chan_width,
287
291
const int y_chan_width,
288
- const int Fc,
289
292
const enum e_directionality directionality);
290
293
291
294
static void load_perturbed_connection_block_pattern (vtr::NdMatrix<int , 6 >& tracks_connected_to_pin,
@@ -1144,7 +1147,7 @@ static void build_rr_graph(const t_graph_type graph_type,
1144
1147
segment_inf[k].name .c_str (),
1145
1148
Fc_out[i][j][k],
1146
1149
Fc_in[i][j][k]);
1147
- #endif /* VERBOSE */
1150
+ #endif
1148
1151
VTR_ASSERT_MSG (Fc_out[i][j][k] == 0 || Fc_in[i][j][k] == 0 ,
1149
1152
" Pins must be inputs or outputs (i.e. can not have both non-zero Fc_out and Fc_in)" );
1150
1153
}
@@ -3259,7 +3262,7 @@ static vtr::NdMatrix<std::vector<int>, 5> alloc_and_load_pin_to_track_map(const
3259
3262
}
3260
3263
3261
3264
/* get pin connections to tracks of the current segment type */
3262
- auto pin_to_seg_type_map = alloc_and_load_pin_to_seg_type (pin_type, num_seg_type_tracks, max_Fc, Type, type_layer, perturb_switch_pattern[seg_inf[iseg].seg_index ], directionality);
3265
+ auto pin_to_seg_type_map = alloc_and_load_pin_to_seg_type (pin_type, Fc, num_seg_type_tracks, seg_inf[iseg]. seg_index , max_Fc, Type, type_layer, perturb_switch_pattern[seg_inf[iseg].seg_index ], directionality);
3263
3266
3264
3267
/* connections in pin_to_seg_type_map are within that seg type -- i.e. in the [0,num_seg_type_tracks-1] range.
3265
3268
* now load up 'result' array with these connections, but offset them so they are relative to the channel
@@ -3296,8 +3299,10 @@ static vtr::NdMatrix<std::vector<int>, 5> alloc_and_load_pin_to_track_map(const
3296
3299
}
3297
3300
3298
3301
static vtr::NdMatrix<int , 6 > alloc_and_load_pin_to_seg_type (const e_pin_type pin_type,
3302
+ const vtr::Matrix<int >& Fc,
3299
3303
const int num_seg_type_tracks,
3300
- const int Fc,
3304
+ const int seg_index,
3305
+ const int max_Fc,
3301
3306
const t_physical_tile_type_ptr Type,
3302
3307
const std::set<int > type_layer,
3303
3308
const bool perturb_switch_pattern,
@@ -3331,7 +3336,7 @@ static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin
3331
3336
size_t (Type->height ), // [0..height-1]
3332
3337
size_t (grid.get_num_layers ()), // [0..layer-1]
3333
3338
NUM_SIDES, // [0..NUM_SIDES-1]
3334
- size_t (Fc ) // [0..Fc-1]
3339
+ size_t (max_Fc ) // [0..Fc-1]
3335
3340
},
3336
3341
OPEN); // Unconnected
3337
3342
@@ -3471,11 +3476,11 @@ static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin
3471
3476
if (perturb_switch_pattern) {
3472
3477
load_perturbed_connection_block_pattern (tracks_connected_to_pin,
3473
3478
pin_ordering,
3474
- num_seg_type_tracks, num_seg_type_tracks, Fc , directionality);
3479
+ num_seg_type_tracks, num_seg_type_tracks, max_Fc , directionality);
3475
3480
} else {
3476
3481
load_uniform_connection_block_pattern (tracks_connected_to_pin,
3477
- pin_ordering,
3478
- num_seg_type_tracks, num_seg_type_tracks, Fc, directionality);
3482
+ pin_ordering, Fc, seg_index,
3483
+ num_seg_type_tracks, num_seg_type_tracks, directionality);
3479
3484
}
3480
3485
3481
3486
#ifdef ENABLE_CHECK_ALL_TRACKS
@@ -3620,9 +3625,10 @@ static float pattern_fmod(float a, float b) {
3620
3625
3621
3626
static void load_uniform_connection_block_pattern (vtr::NdMatrix<int , 6 >& tracks_connected_to_pin,
3622
3627
const std::vector<t_pin_loc>& pin_locations,
3628
+ const vtr::Matrix<int >& Fc,
3629
+ const int seg_index,
3623
3630
const int x_chan_width,
3624
3631
const int y_chan_width,
3625
- const int Fc,
3626
3632
enum e_directionality directionality) {
3627
3633
/* Loads the tracks_connected_to_pin array with an even distribution of *
3628
3634
* switches across the tracks for each pin. For example, each pin connects *
@@ -3700,7 +3706,7 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
3700
3706
group_size = 2 ;
3701
3707
}
3702
3708
3703
- VTR_ASSERT ((x_chan_width % group_size == 0 ) && (y_chan_width % group_size == 0 ) && (Fc % group_size == 0 ) );
3709
+ VTR_ASSERT ((x_chan_width % group_size == 0 ) && (y_chan_width % group_size == 0 ));
3704
3710
3705
3711
/* offset is used to move to a different point in the track space if it is detected that
3706
3712
* the tracks being assigned overlap recently assigned tracks, with the goal of increasing
@@ -3714,19 +3720,23 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
3714
3720
int width = pin_locations[i].width_offset ;
3715
3721
int height = pin_locations[i].height_offset ;
3716
3722
int layer = pin_locations[i].layer_offset ;
3723
+ int pin_fc = Fc[pin][seg_index];
3724
+
3725
+ VTR_ASSERT (pin_fc % group_size == 0 );
3726
+ VTR_LOG (" pin %d, side %d, width %d, height %d, layer %d, pin_fc %d\n " , pin, side, width, height, layer, pin_fc);
3717
3727
3718
3728
/* Bi-directional treats each track separately, uni-directional works with pairs of tracks */
3719
- for (int j = 0 ; j < (Fc / group_size); ++j) {
3729
+ for (int j = 0 ; j < (pin_fc / group_size); ++j) {
3720
3730
int max_chan_width = (((side == TOP) || (side == BOTTOM)) ? x_chan_width : y_chan_width);
3721
3731
3722
3732
// if the number of tracks we can assign is zero break from the loop
3723
3733
if (max_chan_width == 0 ) {
3724
3734
break ;
3725
3735
}
3726
- float step_size = (float )max_chan_width / (float )(Fc * num_phys_pins);
3736
+ float step_size = (float )max_chan_width / (float )(pin_fc * num_phys_pins);
3727
3737
3728
- VTR_ASSERT (Fc > 0 );
3729
- float fc_step = (float )max_chan_width / (float )Fc ;
3738
+ VTR_ASSERT (pin_fc > 0 );
3739
+ float fc_step = (float )max_chan_width / (float )pin_fc ;
3730
3740
3731
3741
/* We may go outside the track ID space, because of offset, so use modulo arithmetic below. */
3732
3742
@@ -3753,7 +3763,7 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
3753
3763
int num_unassigned_tracks = 0 ;
3754
3764
int num_total_tracks = 0 ;
3755
3765
3756
- for (int j2 = 0 ; j2 < (Fc / group_size); ++j2) {
3766
+ for (int j2 = 0 ; j2 < (pin_fc / group_size); ++j2) {
3757
3767
ftrack = pattern_fmod ((i + offset + offset_increment) * step_size, fc_step) + (j2 * fc_step);
3758
3768
itrack = ((int )ftrack) * group_size;
3759
3769
0 commit comments