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add comments for HBM-style traffoc flow files
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‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_16_noc_2way_ring.flows

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<traffic_flows>
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<!--
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In this benchmark, each NoC routers sends traffic flows to two
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NoC routers after itself. These two traffic flows cannot share the
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same NoC link without causing congestion. Therefore, they should be
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routed without using any shared links. This benchmark is a simple
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sanity check for congestion-aware NoC placement and traffic flow routing
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algorithms.
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-->
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<single_flow src=".*noc_router_adapter_block_1[^\d].*" dst=".*noc_router_adapter_block_2.*" bandwidth="7e5" />
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<single_flow src=".*noc_router_adapter_block_2.*" dst=".*noc_router_adapter_block_3.*" bandwidth="7e5" />
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<single_flow src=".*noc_router_adapter_block_3.*" dst=".*noc_router_adapter_block_4.*" bandwidth="7e5" />

‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_4_noc_2way_ring.flows

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<traffic_flows>
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<!--
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In this benchmark, each NoC routers sends traffic flows to two
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NoC routers after itself. These two traffic flows cannot share the
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same NoC link without causing congestion. Therefore, they should be
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routed without using any shared links. This benchmark is a simple
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sanity check for congestion-aware NoC placement and traffic flow routing
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algorithms.
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-->
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312
<single_flow src=".*noc_router_adapter_block_1.*" dst=".*noc_router_adapter_block_2.*" bandwidth="7e5" />
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<single_flow src=".*noc_router_adapter_block_2.*" dst=".*noc_router_adapter_block_3.*" bandwidth="7e5" />
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<single_flow src=".*noc_router_adapter_block_3.*" dst=".*noc_router_adapter_block_4.*" bandwidth="7e5" />

‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_bucket_sort.flows

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<traffic_flows>
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<!--
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Based on the architecture proposed in [1],
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we lock down 8 NoC routers at two opposite sides of
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the device. Each PE line is a chain of NoC-attached PEs
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starting from one of the bottom NoC routers and ending at
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one of the top routers. There are two fully-connected layers
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that redistribute the data between PE lines, complicating a
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congestion-free mapping. Fixed NoC routers are specified in
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complex_64_noc_bucket_sort.fixed file, which is to be passed
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to VPR by --fix_clusters command line option. Fixed clusters file
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assume that the stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
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architecture with EP4SE820 is selected.
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[1] N. Samardzic, W. Qiao, V. Aggarwal, M.-C. F. Chang, and J. Cong,
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“Bonsai: High-performance adaptive merge tree sorting,” in 2020
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ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), pp. 282–294, IEEE, 2020
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-->
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<single_flow src=".*noc_router_adapter_block_1[^\d].*" dst=".*noc_router_adapter_block_2[^\d].*" bandwidth="1e6" />
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<single_flow src=".*noc_router_adapter_block_2[^\d].*" dst=".*noc_router_adapter_block_3[^\d].*" bandwidth="1e6" />
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<single_flow src=".*noc_router_adapter_block_5[^\d].*" dst=".*noc_router_adapter_block_6[^\d].*" bandwidth="1e6" />

‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_gaussian_elimination.flows

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<traffic_flows>
22

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<!--
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Inspired by the triangular topology
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introduced in [1], we lock down NoC routers at opposite
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corners of the device, while NoC-attached PEs transmit
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traffic flows in a triangular pattern. When the triangle’s
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dimensions are smaller than the NoC, a congestion-free
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mapping can be easily found. However, in our benchmarks,
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perpendicular sides of the triangle have 11 NoC routers
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while the FPGA being targeted contains a 10x10 mesh of
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physical NoC routers, making a congestion-free solution
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challenging. Fixed NoC routers are specified in
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complex_64_noc_gaussian_elimination.fixed file, which is to be passed
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to VPR by --fix_clusters command line option. Fixed clusters file
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assume that the stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
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architecture with EP4SE820 is selected.
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[1] J. Wang, L. Guo, and J. Cong, “AutoSA: A polyhedral compiler for
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high-performance systolic arrays on FPGA,” in The 2021 ACM/SIGDA
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International Symposium on Field-Programmable Gate Arrays, pp. 93–
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104, 2021.
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-->
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<single_flow src=".*noc_router_adapter_block_1[^\d].*" dst=".*noc_router_adapter_block_2[^\d].*" bandwidth="1e6" latency_cons="7e-9" />
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<single_flow src=".*noc_router_adapter_block_2[^\d].*" dst=".*noc_router_adapter_block_3[^\d].*" bandwidth="1e6" latency_cons="7e-9" />
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<single_flow src=".*noc_router_adapter_block_3[^\d].*" dst=".*noc_router_adapter_block_4[^\d].*" bandwidth="1e6" latency_cons="7e-9" />

‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_genome_seq.flows

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<traffic_flows>
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<!--
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Inspired by the architecture proposed
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in [1], we lock down two logical NoC routers on opposite
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sides of an FPGA device to emulate hardened memory
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controllers. This benchmark consists of nine processing
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element (PE) lines where multiple NoC-attached PEs are
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connected in a chain. The first fixed NoC router transmits
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traffic flows to the first PE in each line, while the last PE
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in each line transmits a traffic flow to the other fixed NoC
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router. Fixed NoC routers are specified in
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complex_64_noc_genome_seq.fixed file, which is to be passed
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to VPR by --fix_clusters command line option. Fixed clusters file
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assume that the stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
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architecture with EP4SE820 is selected.
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[1] L. Guo, J. Lau, Z. Ruan, P. Wei, and J. Cong, “Hardware acceleration of
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long read pairwise overlapping in genome sequencing: A race between
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FPGA and GPU,” in 2019 IEEE 27th Annual International Symposium on
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Field-Programmable Custom Computing Machines (FCCM),
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pp. 127–135, IEEE, 2019
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-->
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<single_flow src=".*noc_router_adapter_block_1[^\d].*" dst=".*noc_router_adapter_block_2[^\d].*" bandwidth="3.33e5" />
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<single_flow src=".*noc_router_adapter_block_2[^\d].*" dst=".*noc_router_adapter_block_3[^\d].*" bandwidth="1e6" />
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<single_flow src=".*noc_router_adapter_block_3[^\d].*" dst=".*noc_router_adapter_block_4[^\d].*" bandwidth="1e6" />

‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_page_rank.flows

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<traffic_flows>
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<!--
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Similar to the genome sequencing benchmark,
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a logical NoC router, which distributes traffic flows to nine
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PE lines, is locked down at the bottom of the device.
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InterPE traffic flows in each line flow in both directions. At the
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end of each line, a logical NoC router is locked down at the
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top of the device to emulate an external memory interface.
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This traffic flow pattern was inspired by the architecture
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introduced in [1]. Fixed NoC routers are specified in
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complex_64_noc_page_rank.fixed file, which is to be passed
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to VPR by --fix_clusters command line option. Fixed clusters file
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assume that the stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml
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architecture with EP4SE820 is selected.
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[1] Y. Chi, L. Guo, J. Lau, Y.-k. Choi, J. Wang, and J. Cong, “Extending
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high-level synthesis for task-parallel programs,” in 2021 IEEE 29th
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Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 204–213, IEEE, 2021.
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-->
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<single_flow src=".*noc_router_adapter_block_1[^\d].*" dst=".*noc_router_adapter_block_2[^\d].*" bandwidth="3.33e5" />
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<single_flow src=".*noc_router_adapter_block_2[^\d].*" dst=".*noc_router_adapter_block_3[^\d].*" bandwidth="1e6" />
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<single_flow src=".*noc_router_adapter_block_3[^\d].*" dst=".*noc_router_adapter_block_2[^\d].*" bandwidth="1e6" />

‎vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_8_noc_2way_ring.flows

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<traffic_flows>
22

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<!--
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In this benchmark, each NoC routers sends traffic flows to two
5+
NoC routers after itself. These two traffic flows cannot share the
6+
same NoC link without causing congestion. Therefore, they should be
7+
routed without using any shared links. This benchmark is a simple
8+
sanity check for congestion-aware NoC placement and traffic flow routing
9+
algorithms.
10+
-->
11+
312
<single_flow src=".*noc_router_adapter_block_1.*" dst=".*noc_router_adapter_block_2.*" bandwidth="7e5" />
413
<single_flow src=".*noc_router_adapter_block_2.*" dst=".*noc_router_adapter_block_3.*" bandwidth="7e5" />
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<single_flow src=".*noc_router_adapter_block_3.*" dst=".*noc_router_adapter_block_4.*" bandwidth="7e5" />

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