[Router] Added YOYO Routing Budgets Algorithm Option to the CLI and Docs

The option to turn on the YOYO routing budgets algorithm (i.e., using
RCV) was previously missing in both the VPR CLI and the documents, and
this commit fixed the issues.

Additionally, this commit added regression tests for the YOYO option.

Author: ueqri

doc/src/vpr/command_line_usage.rst

@@ -1376,15 +1376,17 @@ The following options are only valid when the router is in timing-driven mode (t
 
     **Default:** ``safe``
 
-.. option:: --routing_budgets_algorithm { disable | minimax | scale_delay }
+.. option:: --routing_budgets_algorithm { disable | minimax | yoyo | scale_delay }
 
     .. warning:: Experimental
 
     Controls how the routing budgets are created. Routing budgets are used to guid VPR's routing algorithm to consider both short path and long path timing constraints :cite:`RCV_algorithm`.
 
     ``disable`` is used to disable the budget feature. This uses the default VPR and ignores hold time constraints.
 
-    ``minimax`` sets the minimum and maximum budgets by distributing the long path and short path slacks depending on the the current delay values. This uses the routing cost valleys and Minimax-PERT algorithm :cite:`minimax_pert,RCV_algorithm`.
+    ``minimax`` sets the minimum and maximum budgets by distributing the long path and short path slacks depending on the the current delay values. This uses the Minimax-PERT algorithm :cite:`minimax_pert`.
+
+    ``yoyo`` allocates budgets using minimax algorithm (as above), and enables hold slack resolution in the router using the Routing Cost Valleys (RCV) algorithm :cite:`RCV_algorithm`.
 
     ``scale_delay`` has the minimum budgets set to 0 and the maximum budgets is set to the delay of a net scaled by the pin criticality (net delay/pin criticality).
 

vpr/src/base/read_options.cpp

@@ -272,7 +272,7 @@ struct RouteBudgetsAlgorithm {
     }
 
     std::vector<std::string> default_choices() {
-        return {"minimax", "scale_delay", "disable"};
+        return {"minimax", "yoyo", "scale_delay", "disable"};
     }
 };
 

vpr/src/route/connection_router.h

@@ -45,7 +45,6 @@ class ConnectionRouter : public ConnectionRouterInterface {
         , router_stats_(nullptr)
         , router_debug_(false) {
         heap_.init_heap(grid);
-        // heap_.set_prune_limit(rr_nodes_.size(), kHeapPruneFactor * rr_nodes_.size());
         only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph);
         rr_node_R_upstream.resize(rr_node_route_inf.size());
         rcv_path_data.resize(rr_node_route_inf.size());

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_budgets/config/config.txt

@@ -0,0 +1,28 @@
+##############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=stereovision3.v
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_fixed_chan_width.txt
+
+# How to parse QoR info
+qor_parse_file=qor_fixed_chan_width.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_fixed_chan_width.txt
+
+# Script parameters
+script_params = --routing_budgets_algorithm yoyo --route_chan_width 100 -sdc_file sdc/samples/stereovision3.sdc
+

vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

@@ -87,3 +87,4 @@ regression_tests/vtr_reg_strong/strong_timing_no_fail
 regression_tests/vtr_reg_strong/strong_noc
 regression_tests/vtr_reg_strong/strong_flat_router
 regression_tests/vtr_reg_strong/strong_routing_constraints
+regression_tests/vtr_reg_strong/strong_yoyo_budgets

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_yoyo_budgets/config/config.txt

@@ -0,0 +1,28 @@
+##############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=stereovision3.v
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_fixed_chan_width.txt
+
+# How to parse QoR info
+qor_parse_file=qor_fixed_chan_width.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_fixed_chan_width.txt
+
+# Script parameters
+script_params = -start odin --routing_budgets_algorithm yoyo --route_chan_width 100 -sdc_file sdc/samples/stereovision3.sdc
+

vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt

@@ -82,3 +82,4 @@ regression_tests/vtr_reg_strong_odin/koios_test
 regression_tests/vtr_reg_strong_odin/koios_test_no_hb
 regression_tests/vtr_reg_strong_odin/strong_timing_fail
 regression_tests/vtr_reg_strong_odin/strong_timing_no_fail
+regression_tests/vtr_reg_strong_odin/strong_yoyo_budgets