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lines changed Original file line number Diff line number Diff line change @@ -11,7 +11,6 @@ archs_dir=arch/
1111# Add circuits to list to sweep
1212circuit_list_add=verilog/multiclock_output_and_latch.v
1313circuit_list_add=verilog/multiclock_reader_writer.v
14- circuit_list_add=verilog/multiclock_separate_and_latch.v
1514
1615# Add architectures to list to sweep
1716arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets
2- timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 28.48 vpr 74.37 MiB -1 -1 0.82 29112 2 0.09 -1 -1 37120 -1 -1 30 311 15 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 76152 311 156 1015 1158 1 965 512 28 28 784 memory auto 33.0 MiB 0.67 8099 70.8 MiB 0.86 0.02 4.33535 -3285.96 -4.33535 4.33535 2.50 0.00280388 0.00239864 0.304808 0.261378 40 15073 23 4.25198e+07 9.83682e+06 2.15543e+06 2749.27 16.25 1.29313 1.15413 13732 12 2771 3144 3502108 1542188 4.41448 4.41448 -4444.1 -4.41448 -299.657 -1.22524 2.69266e+06 3434.52 1.02 2.26 0.12685 0.11873 15 950
3- timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 17.93 vpr 73.55 MiB -1 -1 0.81 29096 2 0.10 -1 -1 37336 -1 -1 30 311 15 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 75312 311 156 1015 1158 1 965 512 28 28 784 memory auto 33.4 MiB 0.68 8271 72.6 MiB 0.82 0.01 4.35987 -3335.22 -4.35987 4.35987 2.46 0.00281134 0.00240047 0.293728 0.25155 40 15097 19 4.25198e+07 9.83682e+06 2.19000e+06 2793.37 6.37 1.12928 1.00156 13935 13 2814 3239 2670799 714133 4.46683 4.46683 -3900.1 -4.46683 -270.62 -1.42215 2.74289e+06 3498.59 0.99 1.87 0.136837 0.128021 15 950
4- timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 36.02 vpr 78.44 MiB -1 -1 0.83 28908 2 0.10 -1 -1 37440 -1 -1 30 311 15 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 80320 311 156 1015 1158 1 965 512 28 28 784 memory auto 33.3 MiB 0.69 8464 71.0 MiB 0.86 0.01 4.46267 -3505.94 -4.46267 4.46267 2.34 0.0028001 0.00239829 0.307975 0.263303 40 16956 24 4.25198e+07 9.83682e+06 2.15085e+06 2743.43 23.39 1.25764 1.12333 15739 14 2766 3161 6657207 4939138 5.49524 5.49524 -4433.28 -5.49524 -1531.24 -3.23871 2.68809e+06 3428.68 0.88 3.28 0.137686 0.128538 15 950
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets
2+ timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.96 vpr 62.98 MiB -1 -1 0.09 17312 1 0.06 -1 -1 32012 -1 -1 2 6 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64488 6 1 16 17 2 10 9 4 4 16 clb auto 24.4 MiB 0.01 17 27 11 11 5 63.0 MiB 0.00 0.00 0.876768 -3.49779 -0.876768 0.805 0.01 3.1307e-05 2.4383e-05 0.00025701 0.000223838 20 20 4 107788 107788 10441.3 652.579 0.03 0.00264684 0.0022844 750 1675 -1 16 2 9 9 138 81 0 0 138 81 9 9 0 0 21 14 0 0 22 21 0 0 9 9 0 0 47 16 0 0 30 12 0 0 9 0 0 0 0 0 9 0 0 1.18166 0.805 -4.08984 -1.18166 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00123192 0.0011725 3 7
3+ timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_reader_writer.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.99 vpr 63.57 MiB -1 -1 0.13 17352 1 0.05 -1 -1 31956 -1 -1 2 3 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65092 3 -1 37 33 2 5 5 4 4 16 clb auto 25.1 MiB 0.01 2 12 2 3 7 63.6 MiB 0.00 0.00 1.45 -12.415 -1.45 1.45 0.01 7.4157e-05 6.5884e-05 0.00073152 0.000685799 8 1 1 107788 107788 4888.88 305.555 0.03 0.00414727 0.00381017 630 907 -1 1 1 1 1 10 6 0 0 10 6 1 1 0 0 2 1 0 0 2 2 0 0 1 1 0 0 3 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1.45 1.45 -12.4256 -1.45 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00230166 0.00221666 4 1
4+ timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.94 vpr 63.10 MiB -1 -1 0.11 17224 1 0.04 -1 -1 32076 -1 -1 2 6 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64612 6 1 16 17 2 10 9 4 4 16 clb auto 24.5 MiB 0.01 17 27 11 11 5 63.1 MiB 0.00 0.00 0.876768 -3.49779 -0.876768 0.805 0.01 3.0833e-05 2.4016e-05 0.00026753 0.000229748 20 20 4 107788 107788 10441.3 652.579 0.03 0.00264032 0.00227948 750 1675 -1 16 2 9 9 138 81 0 0 138 81 9 9 0 0 21 14 0 0 22 21 0 0 9 9 0 0 47 16 0 0 30 12 0 0 9 0 0 0 0 0 9 0 0 1.18166 0.805 -4.08984 -1.18166 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00130013 0.00124058 3 7
5+ timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_reader_writer.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 1.05 vpr 63.22 MiB -1 -1 0.12 17316 1 0.07 -1 -1 31904 -1 -1 2 3 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64736 3 -1 37 33 2 5 5 4 4 16 clb auto 24.7 MiB 0.01 2 12 2 3 7 63.2 MiB 0.00 0.00 1.45 -12.415 -1.45 1.45 0.01 7.3744e-05 6.5654e-05 0.000749719 0.000704822 8 1 1 107788 107788 4888.88 305.555 0.04 0.00597601 0.0053587 630 907 -1 1 1 1 1 10 6 0 0 10 6 1 1 0 0 2 1 0 0 2 2 0 0 1 1 0 0 3 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1.45 1.45 -12.4256 -1.45 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00228134 0.00219433 4 1
6+ timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.95 vpr 62.97 MiB -1 -1 0.09 17304 1 0.04 -1 -1 32016 -1 -1 2 6 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64480 6 1 16 17 2 10 9 4 4 16 clb auto 24.4 MiB 0.01 17 27 11 11 5 63.0 MiB 0.00 0.00 0.876768 -3.49779 -0.876768 0.805 0.01 4.2225e-05 3.2683e-05 0.000268149 0.00023055 20 20 4 107788 107788 10441.3 652.579 0.03 0.00272828 0.00235235 750 1675 -1 16 2 9 9 138 81 0 0 138 81 9 9 0 0 21 14 0 0 22 21 0 0 9 9 0 0 47 16 0 0 30 12 0 0 9 0 0 0 0 0 9 0 0 1.18166 0.805 -4.08984 -1.18166 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00127069 0.00121218 3 7
7+ timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_reader_writer.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.96 vpr 63.20 MiB -1 -1 0.11 17440 1 0.04 -1 -1 31944 -1 -1 2 3 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64712 3 -1 37 33 2 5 5 4 4 16 clb auto 24.6 MiB 0.01 2 12 2 3 7 63.2 MiB 0.00 0.00 1.45 -12.415 -1.45 1.45 0.01 7.268e-05 6.4675e-05 0.000730213 0.000686149 8 1 1 107788 107788 4888.88 305.555 0.03 0.00422287 0.00388435 630 907 -1 1 1 1 1 10 6 0 0 10 6 1 1 0 0 2 1 0 0 2 2 0 0 1 1 0 0 3 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1.45 1.45 -12.4256 -1.45 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00231144 0.00222596 4 1
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