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[core] debug
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vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -868,7 +868,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
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break;
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case RIGHT:
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/* Consider the routing channel that is connected to the top side of the switch block */
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chan_side = TOP;
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chan_side = BOTTOM;
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/* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */
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ix = rr_gsb.get_sb_x() + 1;
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iy = rr_gsb.get_sb_y();
@@ -884,7 +884,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
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break;
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case LEFT:
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/* Consider the routing channel that is connected to the top side of the switch block */
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chan_side = TOP;
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chan_side = BOTTOM;
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/* The input pins of the routing channel come from the right side of Grid[x][y+1] */
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ix = rr_gsb.get_sb_x();
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iy = rr_gsb.get_sb_y();

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