[Pack] Cleaned Up try_pack API

The try_pack API required an approximation for the inter-cluster delay;
however, this approximation was always being made the same way and did
not need to be brought in externally. Inlined this into the packer
itself to make the interface easier to work with.

Author: AlexandreSinger

vpr/src/base/vpr_api.cpp

@@ -109,12 +109,6 @@ static void free_complex_block_types();
 static void free_device(const t_det_routing_arch& routing_arch);
 static void free_circuit();
 
-static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup,
-                                                    const t_arch& arch,
-                                                    const int wire_segment_length,
-                                                    int* opin_switch_fanin,
-                                                    int* wire_switch_fanin,
-                                                    int* ipin_switch_fanin);
 /* Local subroutines end */
 
 ///@brief Display general VPR information
@@ -641,53 +635,6 @@ bool vpr_pack_flow(t_vpr_setup& vpr_setup, const t_arch& arch) {
 bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) {
     vtr::ScopedStartFinishTimer timer("Packing");
 
-    /* If needed, estimate inter-cluster delay. Assume the average routing hop goes out of
-     * a block through an opin switch to a length-4 wire, then through a wire switch to another
-     * length-4 wire, then through a wire-to-ipin-switch into another block. */
-    int wire_segment_length = 4;
-
-    float inter_cluster_delay = UNDEFINED;
-    if (vpr_setup.PackerOpts.timing_driven
-        && vpr_setup.PackerOpts.auto_compute_inter_cluster_net_delay) {
-        /* We want to determine a reasonable fan-in to the opin, wire, and ipin switches, based
-         * on which the intercluster delays can be estimated. The fan-in of a switch influences its
-         * delay.
-         *
-         * The fan-in of the switch depends on the architecture (unidirectional/bidirectional), as
-         * well as Fc_in/out and Fs */
-        int opin_switch_fanin, wire_switch_fanin, ipin_switch_fanin;
-        get_intercluster_switch_fanin_estimates(vpr_setup, arch, wire_segment_length, &opin_switch_fanin,
-                                                &wire_switch_fanin, &ipin_switch_fanin);
-
-        float Tdel_opin_switch, R_opin_switch, Cout_opin_switch;
-        float opin_switch_del = get_arch_switch_info(arch.Segments[0].arch_opin_switch, opin_switch_fanin,
-                                                     Tdel_opin_switch, R_opin_switch, Cout_opin_switch);
-
-        float Tdel_wire_switch, R_wire_switch, Cout_wire_switch;
-        float wire_switch_del = get_arch_switch_info(arch.Segments[0].arch_wire_switch, wire_switch_fanin,
-                                                     Tdel_wire_switch, R_wire_switch, Cout_wire_switch);
-
-        float Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch;
-        float wtoi_switch_del = get_arch_switch_info(vpr_setup.RoutingArch.wire_to_arch_ipin_switch, ipin_switch_fanin,
-                                                     Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch);
-
-        float Rmetal = arch.Segments[0].Rmetal;
-        float Cmetal = arch.Segments[0].Cmetal;
-
-        /* The delay of a wire with its driving switch is the switch delay plus the
-         * product of the equivalent resistance and capacitance experienced by the wire. */
-
-        float first_wire_seg_delay = opin_switch_del
-                                     + (R_opin_switch + Rmetal * (float)wire_segment_length / 2)
-                                           * (Cout_opin_switch + Cmetal * (float)wire_segment_length);
-        float second_wire_seg_delay = wire_switch_del
-                                      + (R_wire_switch + Rmetal * (float)wire_segment_length / 2)
-                                            * (Cout_wire_switch + Cmetal * (float)wire_segment_length);
-        inter_cluster_delay = 4
-                              * (first_wire_seg_delay + second_wire_seg_delay
-                                 + wtoi_switch_del); /* multiply by 4 to get a more conservative estimate */
-    }
-
     // Read in the flat placement if a flat placement file is provided and it
     // has not been loaded already.
     if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() &&
@@ -698,8 +645,9 @@ bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) {
     }
 
     return try_pack(&vpr_setup.PackerOpts, &vpr_setup.AnalysisOpts,
-                    &arch, vpr_setup.user_models,
-                    vpr_setup.library_models, inter_cluster_delay,
+                    arch, vpr_setup.RoutingArch,
+                    vpr_setup.user_models,
+                    vpr_setup.library_models,
                     vpr_setup.PackerRRGraph, g_vpr_ctx.atom().flat_placement_info);
 }
 
@@ -1212,100 +1160,6 @@ void vpr_close_graphics(const t_vpr_setup& /*vpr_setup*/) {
     free_draw_structs();
 }
 
-/**
- * Since the parameters of a switch may change as a function of its fanin,
- * to get an estimation of inter-cluster delays we need a reasonable estimation
- * of the fan-ins of switches that connect clusters together. These switches are
- * 1) opin to wire switch
- * 2) wire to wire switch
- * 3) wire to ipin switch
- * We can estimate the fan-in of these switches based on the Fc_in/Fc_out of
- * a logic block, and the switch block Fs value
- */
-static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup,
-                                                    const t_arch& arch,
-                                                    const int wire_segment_length,
-                                                    int* opin_switch_fanin,
-                                                    int* wire_switch_fanin,
-                                                    int* ipin_switch_fanin) {
-    e_directionality directionality;
-    int Fs;
-    float Fc_in, Fc_out;
-    int W = 100; //W is unknown pre-packing, so *if* we need W here, we will assume a value of 100
-
-    directionality = vpr_setup.RoutingArch.directionality;
-    Fs = vpr_setup.RoutingArch.Fs;
-    Fc_in = 0, Fc_out = 0;
-
-    //Build a dummy 10x10 device to determine the 'best' block type to use
-    auto grid = create_device_grid(vpr_setup.device_layout, arch.grid_layouts, 10, 10);
-
-    auto type = find_most_common_tile_type(grid);
-    /* get Fc_in/out for most common block (e.g. logic blocks) */
-    VTR_ASSERT(!type->fc_specs.empty());
-
-    //Estimate the maximum Fc_in/Fc_out
-
-    for (const t_fc_specification& fc_spec : type->fc_specs) {
-        float Fc = fc_spec.fc_value;
-
-        if (fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE) {
-            //Convert to estimated fractional
-            Fc /= W;
-        }
-        VTR_ASSERT_MSG(Fc >= 0 && Fc <= 1., "Fc should be fractional");
-
-        for (int ipin : fc_spec.pins) {
-            e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, ipin);
-
-            if (pin_type == DRIVER) {
-                Fc_out = std::max(Fc, Fc_out);
-            } else {
-                VTR_ASSERT(pin_type == RECEIVER);
-                Fc_in = std::max(Fc, Fc_in);
-            }
-        }
-    }
-
-    /* Estimates of switch fan-in are done as follows:
-     * 1) opin to wire switch:
-     * 2 CLBs connect to a channel, each with #opins/4 pins. Each pin has Fc_out*W
-     * switches, and then we assume the switches are distributed evenly over the W wires.
-     * In the unidirectional case, all these switches are then crammed down to W/wire_segment_length wires.
-     *
-     * Unidirectional: 2 * #opins_per_side * Fc_out * wire_segment_length
-     * Bidirectional:  2 * #opins_per_side * Fc_out
-     *
-     * 2) wire to wire switch
-     * A wire segment in a switchblock connects to Fs other wires. Assuming these connections are evenly
-     * distributed, each target wire receives Fs connections as well. In the unidirectional case,
-     * source wires can only connect to W/wire_segment_length wires.
-     *
-     * Unidirectional: Fs * wire_segment_length
-     * Bidirectional:  Fs
-     *
-     * 3) wire to ipin switch
-     * An input pin of a CLB simply receives Fc_in connections.
-     *
-     * Unidirectional: Fc_in
-     * Bidirectional:  Fc_in
-     */
-
-    /* Fan-in to opin/ipin/wire switches depends on whether the architecture is unidirectional/bidirectional */
-    (*opin_switch_fanin) = 2 * type->num_drivers / 4 * Fc_out;
-    (*wire_switch_fanin) = Fs;
-    (*ipin_switch_fanin) = Fc_in;
-    if (directionality == UNI_DIRECTIONAL) {
-        /* adjustments to opin-to-wire and wire-to-wire switch fan-ins */
-        (*opin_switch_fanin) *= wire_segment_length;
-        (*wire_switch_fanin) *= wire_segment_length;
-    } else if (directionality == BI_DIRECTIONAL) {
-        /* no adjustments need to be made here */
-    } else {
-        VPR_FATAL_ERROR(VPR_ERROR_PACK, "Unrecognized directionality: %d\n", (int)directionality);
-    }
-}
-
 ///@brief Free architecture data structures
 void free_device(const t_det_routing_arch& /*routing_arch*/) {
     auto& device_ctx = g_vpr_ctx.mutable_device();