File tree 2 files changed +8
-8
lines changed
vtr_flow/tasks/regression_tests/vtr_reg_strong
strong_place_delay_calc_method/config
strong_place_delay_model/config
2 files changed +8
-8
lines changed Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 34.84 vpr 975.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/ vtr-verilog-to-routing/vtr_flow/tasks 998768 10 10 168 178 1 68 30 11 8 88 io auto 952.5 MiB 0.50 358 812 97 660 55 975.4 MiB 0.07 0.00 6.44563 -69.2664 -6.44563 6.44563 3.31 0.000633306 0.000584828 0.014981 0.013961 26 784 31 0 0 125464. 1425.72 1.77 0.217747 0.184211 11500 28430 -1 625 17 282 1013 95514 35394 6.59221 6.59221 -74.0805 -6.59221 0 0 163463. 1857.53 0.03 0.07 0.09 -1 -1 0.03 0.0275927 0.0245705
3- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 34.42 vpr 975.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/ vtr-verilog-to-routing/vtr_flow/tasks 998944 10 10 168 178 1 68 30 11 8 88 io auto 952.6 MiB 0.50 365 812 101 651 60 975.5 MiB 0.10 0.00 6.37156 -69.5088 -6.37156 6.37156 3.32 0.000634379 0.000586337 0.015972 0.0149437 24 851 26 0 0 114778. 1304.29 1.37 0.179349 0.152804 11416 27150 -1 691 14 354 1388 135595 52969 6.82221 6.82221 -75.6812 -6.82221 0 0 153433. 1743.56 0.03 0.07 0.09 -1 -1 0.03 0.024931 0.0223273
4- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 35.84 vpr 975.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/ vtr-verilog-to-routing/vtr_flow/tasks 998788 10 10 168 178 1 68 30 11 8 88 io auto 952.4 MiB 0.50 367 812 86 668 58 975.4 MiB 0.15 0.00 6.39336 -69.4912 -6.39336 6.39336 4.34 0.000639177 0.000587378 0.017224 0.0162017 22 875 22 0 0 110609. 1256.92 1.66 0.199683 0.169442 11258 24748 -1 730 18 335 1182 109582 46429 6.92426 6.92426 -76.9247 -6.92426 0 0 134428. 1527.59 0.02 0.07 0.09 -1 -1 0.02 0.0283942 0.0252052
5- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 35.35 vpr 975.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/ vtr-verilog-to-routing/vtr_flow/tasks 998932 10 10 168 178 1 68 30 11 8 88 io auto 952.8 MiB 0.50 368 812 78 675 59 975.5 MiB 0.07 0.00 6.26392 -68.4373 -6.26392 6.26392 4.33 0.000637702 0.000588521 0.0149562 0.0139792 28 776 45 0 0 134428. 1527.59 1.48 0.227998 0.19302 11590 29630 -1 595 13 254 987 91515 32222 6.61176 6.61176 -72.652 -6.61176 0 0 173354. 1969.93 0.03 0.07 0.10 -1 -1 0.03 0.0241301 0.021664
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 27.50 vpr 977.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 0f69adb Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.5 .0-1025-azure x86_64 2024-10-15T16:01:56 fv-az837-567 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 1001044 10 10 168 178 1 68 30 11 8 88 io auto 956.2 MiB 0.45 370 858 95 697 66 977.6 MiB 0.04 0.00 6.45248 -69.1493 -6.45248 6.45248 2.68 0.000346945 0.000301901 0.0109124 0.00985616 -1 -1 -1 -1 32 693 33 0 0 153433. 1743.56 1.19 0.127615 0.111696 11830 34246 -1 570 10 235 725 56242 26416 6.94346 6.94346 -73.9579 -6.94346 0 0 205860. 2339.32 0.06 0.04 0.08 -1 -1 0.06 0.0194505 0.0184001
3+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 27.82 vpr 977.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 0f69adb Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.5 .0-1025-azure x86_64 2024-10-15T16:01:56 fv-az837-567 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 1000804 10 10 168 178 1 68 30 11 8 88 io auto 954.9 MiB 0.45 369 812 82 656 74 977.3 MiB 0.04 0.00 6.45248 -69.2479 -6.45248 6.45248 2.74 0.00035978 0.000313724 0.0101986 0.00925468 -1 -1 -1 -1 32 691 29 0 0 153433. 1743.56 1.24 0.130899 0.114171 11830 34246 -1 553 12 224 697 51846 24062 6.94346 6.94346 -73.4811 -6.94346 0 0 205860. 2339.32 0.06 0.04 0.08 -1 -1 0.06 0.0206713 0.0194697
4+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 28.08 vpr 977.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 0f69adb Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.5 .0-1025-azure x86_64 2024-10-15T16:01:56 fv-az837-567 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 1001124 10 10 168 178 1 68 30 11 8 88 io auto 955.1 MiB 0.47 370 812 89 663 60 977.7 MiB 0.04 0.00 6.52191 -68.7563 -6.52191 6.52191 3.40 0.000347877 0.0002958 0.010332 0.00933957 -1 -1 -1 -1 22 809 21 0 0 110609. 1256.92 0.45 0.066663 0.0592234 11258 24748 -1 663 14 329 1173 67735 35710 7.04515 7.04515 -76.4932 -7.04515 0 0 134428. 1527.59 0.04 0.05 0.07 -1 -1 0.04 0.0237505 0.0223282
5+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 28.29 vpr 977.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 0f69adb Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.5 .0-1025-azure x86_64 2024-10-15T16:01:56 fv-az837-567 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 1001072 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.45 368 812 95 656 61 977.6 MiB 0.04 0.00 6.34478 -68.8031 -6.34478 6.34478 3.48 0.000358527 0.000311549 0.0101593 0.00922939 -1 -1 -1 -1 28 753 22 0 0 134428. 1527.59 0.44 0.0663655 0.0590372 11590 29630 -1 624 15 260 959 55378 26467 6.64742 6.64742 -72.827 -6.64742 0 0 173354. 1969.93 0.05 0.04 0.07 -1 -1 0.05 0.0225106 0.0210004
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 36.49 vpr 976.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 06e69833b release VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-24T21 :01:36 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/ vtr-verilog-to-routing 999972 10 10 168 178 1 68 30 11 8 88 io auto 953.5 MiB 0.53 379 582 84 459 39 976.5 MiB 0.08 0.00 6.38543 -68.9302 -6.38543 6.38543 3.85 0.00117056 0.00108398 0.0191957 0.0180156 30 733 26 0 0 144567. 1642.81 1.72 0.412078 0.372155 11730 32605 -1 595 15 304 1303 77064 35227 6.62321 6.62321 -73.1566 -6.62321 0 0 194014. 2204.70 0.04 0.09 0.13 -1 -1 0.04 0.0430054 0.0396466
3- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 36.53 vpr 976.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 06e69833b release VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-24T21 :01:36 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/ vtr-verilog-to-routing 999900 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.51 402 582 89 465 28 976 .5 MiB 0.08 0.00 6.38543 -69.465 -6.38543 6.38543 3.85 0.00117584 0.00109024 0.0188446 0.0177126 26 876 20 0 0 125464. 1425.72 2.46 0.460152 0.415471 11500 28430 -1 736 13 335 1253 78094 39338 6.89777 6.89777 -75.7093 -6.89777 0 0 163463. 1857.53 0.03 0.06 0.09 -1 -1 0.03 0.0204322 0.0190272
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 28.29 vpr 977.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 0f69adb Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.5 .0-1025-azure x86_64 2024-10-15T16 :01:56 fv-az837-567 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 1001196 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.43 393 628 105 491 32 977.7 MiB 0.03 0.00 6.51193 -69.1178 -6.51193 6.51193 2.64 0.000368496 0.000316279 0.00897708 0.00821508 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 1.58 0.129641 0.112291 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 125464. 1425.72 0.04 0.06 0.07 -1 -1 0.04 0.0265283 0.0245474
3+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 28.12 vpr 977.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 0f69adb Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.5 .0-1025-azure x86_64 2024-10-15T16 :01:56 fv-az837-567 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 1000956 10 10 168 178 1 68 30 11 8 88 io auto 955.9 MiB 0.54 380 628 91 496 41 977 .5 MiB 0.05 0.00 6.52338 -69.1003 -6.52338 6.52338 2.70 0.000355671 0.000305949 0.00939391 0.00863885 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 1.15 0.113164 0.0991248 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.08 0.05 0.08 -1 -1 0.08 0.0197747 0.0187602
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