Submitting Koios benchmarks

Author: aman26kbm

doc/src/vtr/benchmarks.rst

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     spla        2278
     tseng       1583
     =========   ========================================
+

doc/src/z_references.bib

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 	number={},
 	pages={1-1}
 }
+<<<<<<< HEAD
+=======
+
+@inproceedings{koios_benchmarks,
+  title={Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research},
+  author={Arora, Aman and Boutros, Andrew and Rauch, Daniel and Rajen, Aishwarya and Borda, Aatman and Damghani, Seyed A. and Mehta, Samidh and Kate, Sangram and Patel, Pragnesh and Kent, Kenneth B. and Betz, Vaughn and John, Lizy K.},
+  booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
+  year={2021}
+}
+
+>>>>>>> ca872deda... Dummy change to create a new commit for all files to be PR'ed

vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml

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+# Koios Benchmarks
+
+## Introduction
+Koios benchmarks are a set of Deep Learning (DL) benchmarks for FPGA architecture and CAD research. They are suitable for DL related architecture and CAD research. There are 19 designs that include several medium-sized benchmarks and some large benchmarks. The designs target different network types (CNNs, RNNs, MLPs, RL) and layer types (fully-connected, convolution, activation, softmax, reduction, eltwise). Some of the designs are generated from HLS tools as well. These designs use many precisions including binary, different fixed point types int8/16/32, brain floating point (bfloat16), and IEEE half-precision floating point (fp16).
+
+## Documentation
+A brief documentation of Koios benchmarks is available [here](https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/#koios-benchmarks).
+
+## How to Cite
+The following paper may be used as a citation for Koios:
+
+A. Arora, A. Boutros, D. Rauch, A. Rajen, A. Borda, S. A. Damghani, S. Mehta, S. Kate, P. Patel, K. B. Kent, V. Betz, L. K. John "Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research", FPL, 2021.
+
+Bibtex:
+```
+@inproceedings{koios_benchmarks,
+  title={Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research},
+  author={Arora, Aman and Boutros, Andrew and Rauch, Daniel and Rajen, Aishwarya and Borda, Aatman and Damghani, Seyed A. and Mehta, Samidh and Kate, Sangram and Patel, Pragnesh and Kent, Kenneth B. and Betz, Vaughn and John, Lizy K.},
+  booktitle={International Conference on Field Programmable Logic and Applications (FPL)},
+  year={2021}
+}
+```
+
+## License
+Koios benchmarks are distributed under the [same license as VTR](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/LICENSE.md). 
+
+## Contact
+If you have questions, email [Aman Arora](mailto:[email protected]). 
+
+If you find any bugs, please file an issue [here](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues) and tag @aman26kbm in the description.
+
+## Contributing to Koios
+We welcome contributions to this benchmark suite. If you'd like to contribute to Koios, contact [Aman Arora](mailto:[email protected]). 
+
+## Contributors
+*Please keep this up-to-date*
+
+**Professors:** Lizy K. John, Vaughn Betz, Kenneth B. Kent
+
+**Doctoral Students:** Aman Arora (University of Texas at Austin), Andrew Boutros (University of Toronto)
+
+**Graduate Students:** Daniel Rauch (University of Texas at Austin), Aishwarya Rajen (University of Texas at Austin), Seyed Alireza Damghani (University of New Brunswick), Sangram Kate (University of Texas at Austin)
+
+**Undergraduate Students:** Aatman Borda (University of Texas at Austin), Samidh Mehta (University of Texas at Austin), Pragnesh Patel (University of Texas at Austin)
+