Skip to content

Commit bb48ec3

Browse files
vaughnbetzvaughnbetz
authored
Merge branch 'master' into fix-missing-include
2 parents ac73008 + 04cd1fd commit bb48ec3

File tree

8 files changed

+216
-35
lines changed

8 files changed

+216
-35
lines changed

‎libs/libarchfpga/src/physical_types_util.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -248,6 +248,7 @@ int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index
248248
int ipin = OPEN;
249249
int port_base_ipin = 0;
250250
int num_pins = OPEN;
251+
int pin_offset = 0;
251252

252253
bool port_found = false;
253254
for (const auto& sub_tile : type->sub_tiles) {
@@ -266,12 +267,13 @@ int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index
266267
}
267268

268269
port_base_ipin = 0;
270+
pin_offset += sub_tile.num_phy_pins;
269271
}
270272

271273
if (num_pins != OPEN) {
272274
VTR_ASSERT(pin_index_in_port < num_pins);
273275

274-
ipin = port_base_ipin + pin_index_in_port;
276+
ipin = port_base_ipin + pin_index_in_port + pin_offset;
275277
}
276278

277279
return ipin;

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4219,9 +4219,9 @@ static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* N
42194219
}
42204220

42214221
/* Check that the direct chain connection is not zero in both direction */
4222-
if ((*Directs)[i].x_offset == 0 && (*Directs)[i].y_offset == 0) {
4222+
if ((*Directs)[i].x_offset == 0 && (*Directs)[i].y_offset == 0 && (*Directs)[i].sub_tile_offset == 0) {
42234223
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
4224-
"The x_offset and y_offset are both zero, this is a length 0 direct chain connection.\n");
4224+
"The x_offset, y_offset, z_offset are all zero, this is a length 0 direct chain connection.\n");
42254225
}
42264226

42274227
(*Directs)[i].line = loc_data.line(Node);

‎vpr/src/route/rr_graph.cpp

Lines changed: 34 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -137,18 +137,18 @@ static void build_unidir_rr_opins(const int i,
137137
const int num_seg_types,
138138
t_opin_connections_scratchpad* scratchpad);
139139

140-
static int get_opin_direct_connecions(int x,
141-
int y,
142-
e_side side,
143-
int opin,
144-
int from_rr_node,
145-
t_rr_edge_info_set& rr_edges_to_create,
146-
const t_rr_node_indices& L_rr_node_indices,
147-
const t_rr_graph_storage& rr_nodes,
148-
const t_direct_inf* directs,
149-
const int num_directs,
150-
const t_clb_to_clb_directs* clb_to_clb_directs,
151-
t_opin_connections_scratchpad* scratchpad);
140+
static int get_opin_direct_connections(int x,
141+
int y,
142+
e_side side,
143+
int opin,
144+
int from_rr_node,
145+
t_rr_edge_info_set& rr_edges_to_create,
146+
const t_rr_node_indices& L_rr_node_indices,
147+
const t_rr_graph_storage& rr_nodes,
148+
const t_direct_inf* directs,
149+
const int num_directs,
150+
const t_clb_to_clb_directs* clb_to_clb_directs,
151+
t_opin_connections_scratchpad* scratchpad);
152152

153153
static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(t_rr_graph_storage& L_rr_node,
154154
const int num_seg_types,
@@ -1328,9 +1328,9 @@ static void build_bidir_rr_opins(const int i,
13281328
}
13291329

13301330
/* Add in direct connections */
1331-
get_opin_direct_connecions(i, j, side, pin_index,
1332-
node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
1333-
directs, num_directs, clb_to_clb_directs, scratchpad);
1331+
get_opin_direct_connections(i, j, side, pin_index,
1332+
node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
1333+
directs, num_directs, clb_to_clb_directs, scratchpad);
13341334
}
13351335
}
13361336

@@ -2573,8 +2573,8 @@ static void build_unidir_rr_opins(const int i, const int j, const e_side side, c
25732573
}
25742574

25752575
/* Add in direct connections */
2576-
get_opin_direct_connecions(i, j, side, pin_index, opin_node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
2577-
directs, num_directs, clb_to_clb_directs, scratchpad);
2576+
get_opin_direct_connections(i, j, side, pin_index, opin_node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
2577+
directs, num_directs, clb_to_clb_directs, scratchpad);
25782578
}
25792579
}
25802580

@@ -2688,18 +2688,18 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
26882688
*
26892689
* The current opin is located at (x,y) along the specified side
26902690
*/
2691-
static int get_opin_direct_connecions(int x,
2692-
int y,
2693-
e_side side,
2694-
int opin,
2695-
int from_rr_node,
2696-
t_rr_edge_info_set& rr_edges_to_create,
2697-
const t_rr_node_indices& L_rr_node_indices,
2698-
const t_rr_graph_storage& rr_nodes,
2699-
const t_direct_inf* directs,
2700-
const int num_directs,
2701-
const t_clb_to_clb_directs* clb_to_clb_directs,
2702-
t_opin_connections_scratchpad* scratchpad) {
2691+
static int get_opin_direct_connections(int x,
2692+
int y,
2693+
e_side side,
2694+
int opin,
2695+
int from_rr_node,
2696+
t_rr_edge_info_set& rr_edges_to_create,
2697+
const t_rr_node_indices& L_rr_node_indices,
2698+
const t_rr_graph_storage& rr_nodes,
2699+
const t_direct_inf* directs,
2700+
const int num_directs,
2701+
const t_clb_to_clb_directs* clb_to_clb_directs,
2702+
t_opin_connections_scratchpad* scratchpad) {
27032703
auto& device_ctx = g_vpr_ctx.device();
27042704

27052705
t_physical_tile_type_ptr curr_type = device_ctx.grid[x][y].type;
@@ -2731,6 +2731,7 @@ static int get_opin_direct_connecions(int x,
27312731
&& y + directs[i].y_offset > 0) {
27322732
//Only add connections if the target clb type matches the type in the direct specification
27332733
t_physical_tile_type_ptr target_type = device_ctx.grid[x + directs[i].x_offset][y + directs[i].y_offset].type;
2734+
27342735
if (clb_to_clb_directs[i].to_clb_type == target_type
27352736
&& z + directs[i].sub_tile_offset < int(target_type->capacity)
27362737
&& z + directs[i].sub_tile_offset >= 0) {
@@ -2765,11 +2766,12 @@ static int get_opin_direct_connecions(int x,
27652766
}
27662767
}
27672768

2769+
int target_sub_tile = z + directs[i].sub_tile_offset;
2770+
if (relative_ipin >= target_type->sub_tiles[target_sub_tile].num_phy_pins) continue;
2771+
27682772
//If this block has capacity > 1 then the pins of z position > 0 are offset
27692773
//by the number of pins per capacity instance
2770-
int ipin = get_physical_pin_from_capacity_location(target_type, relative_ipin, z + directs[i].sub_tile_offset);
2771-
2772-
//if (ipin > target_type->num_pins) continue; //Invalid z-offset
2774+
int ipin = get_physical_pin_from_capacity_location(target_type, relative_ipin, target_sub_tile);
27732775

27742776
/* Add new ipin edge to list of edges */
27752777
std::vector<int>& inodes = scratchpad->scratch[0];

‎vtr_flow/arch/sub_tiles/heterogeneous_tile.xml

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,139 @@
1+
<!-- This architecture definition is a very simplified version to expose usage
2+
of heterogeneous tiles (sub tiles with different IOs and functionalities) -->
3+
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
4+
<models>
5+
<model name="PRIMITIVE">
6+
<input_ports>
7+
<port name="in" combinational_sink_ports="out" />
8+
<port name="in_2" combinational_sink_ports="out_2" />
9+
</input_ports>
10+
<output_ports>
11+
<port name="out"/>
12+
<port name="out_2"/>
13+
</output_ports>
14+
</model>
15+
</models>
16+
<tiles>
17+
<tile name="IO_TILE_WITH_PRIMITIVE">
18+
<sub_tile name="PRIMITIVE_SUB_TILE">
19+
<input name="stub_input" num_pins="25"/>
20+
<input name="primitive_in" num_pins="1"/>
21+
<input name="primitive_in_2" num_pins="1"/>
22+
<output name="stub_output" num_pins="25"/>
23+
<output name="primitive_out" num_pins="1"/>
24+
<output name="primitive_out_2" num_pins="1"/>
25+
<equivalent_sites>
26+
<site pb_type="PRIMITIVE_PB_TYPE" pin_mapping="custom">
27+
<direct from="PRIMITIVE_SUB_TILE.primitive_in" to="PRIMITIVE_PB_TYPE.primitive_in"/>
28+
<direct from="PRIMITIVE_SUB_TILE.primitive_in_2" to="PRIMITIVE_PB_TYPE.primitive_in_2"/>
29+
<direct from="PRIMITIVE_SUB_TILE.primitive_out" to="PRIMITIVE_PB_TYPE.primitive_out"/>
30+
<direct from="PRIMITIVE_SUB_TILE.primitive_out_2" to="PRIMITIVE_PB_TYPE.primitive_out_2"/>
31+
</site>
32+
</equivalent_sites>
33+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
34+
</sub_tile>
35+
<sub_tile name="IPAD_SUB_TILE_0">
36+
<output name="ipad_out_rx_n" num_pins="1"/>
37+
<equivalent_sites>
38+
<site pb_type="IPAD_PB_TYPE"/>
39+
</equivalent_sites>
40+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
41+
</sub_tile>
42+
<sub_tile name="IPAD_SUB_TILE_1">
43+
<output name="ipad_out_rx_p" num_pins="1"/>
44+
<equivalent_sites>
45+
<site pb_type="IPAD_PB_TYPE"/>
46+
</equivalent_sites>
47+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
48+
</sub_tile>
49+
<sub_tile name="OPAD_SUB_TILE_0">
50+
<input name="opad_in_tx_n" num_pins="1"/>
51+
<equivalent_sites>
52+
<site pb_type="OPAD_PB_TYPE"/>
53+
</equivalent_sites>
54+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
55+
</sub_tile>
56+
<sub_tile name="OPAD_SUB_TILE_1">
57+
<input name="opad_in_tx_p" num_pins="1"/>
58+
<equivalent_sites>
59+
<site pb_type="OPAD_PB_TYPE"/>
60+
</equivalent_sites>
61+
<fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
62+
</sub_tile>
63+
</tile>
64+
</tiles>
65+
<complexblocklist>
66+
<pb_type name="PRIMITIVE_PB_TYPE">
67+
<input name="primitive_in" num_pins="1"/>
68+
<input name="primitive_in_2" num_pins="1"/>
69+
<output name="primitive_out" num_pins="1"/>
70+
<output name="primitive_out_2" num_pins="1"/>
71+
<pb_type blif_model=".subckt PRIMITIVE" name="PRIMITIVE" num_pb="1">
72+
<input name="in" num_pins="1"/>
73+
<input name="in_2" num_pins="1"/>
74+
<output name="out" num_pins="1"/>
75+
<output name="out_2" num_pins="1"/>
76+
<delay_constant max="1.667e-9" in_port="PRIMITIVE.in" out_port="PRIMITIVE.out"/>
77+
<delay_constant max="1.667e-9" in_port="PRIMITIVE.in_2" out_port="PRIMITIVE.out_2"/>
78+
</pb_type>
79+
<interconnect>
80+
<direct input="PRIMITIVE_PB_TYPE.primitive_in" name="in" output="PRIMITIVE.in"/>
81+
<direct input="PRIMITIVE_PB_TYPE.primitive_in_2" name="in_2" output="PRIMITIVE.in_2"/>
82+
<direct input="PRIMITIVE.out" name="out" output="PRIMITIVE_PB_TYPE.primitive_out"/>
83+
<direct input="PRIMITIVE.out_2" name="out_2" output="PRIMITIVE_PB_TYPE.primitive_out_2"/>
84+
</interconnect>
85+
</pb_type>
86+
<pb_type name="IPAD_PB_TYPE">
87+
<output name="ipad_out" num_pins="1"/>
88+
<pb_type blif_model=".input" name="IPAD" num_pb="1">
89+
<output name="inpad" num_pins="1"/>
90+
</pb_type>
91+
<interconnect>
92+
<direct input="IPAD.inpad" name="inpad" output="IPAD_PB_TYPE.ipad_out"/>
93+
</interconnect>
94+
</pb_type>
95+
<pb_type name="OPAD_PB_TYPE">
96+
<input name="opad_in" num_pins="1"/>
97+
<pb_type blif_model=".output" name="OPAD" num_pb="1">
98+
<input name="outpad" num_pins="1"/>
99+
</pb_type>
100+
<interconnect>
101+
<direct output="OPAD.outpad" name="outpad" input="OPAD_PB_TYPE.opad_in"/>
102+
</interconnect>
103+
</pb_type>
104+
</complexblocklist>
105+
<layout>
106+
<auto_layout>
107+
<fill type="IO_TILE_WITH_PRIMITIVE" priority="1"/>
108+
<perimeter type="IO_TILE_WITH_PRIMITIVE" priority="1"/>
109+
<corners type="EMPTY" priority="3"/>
110+
</auto_layout>
111+
</layout>
112+
<device>
113+
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
114+
<area grid_logic_tile_area="14813.392"/>
115+
<connection_block input_switch_name="sw"/>
116+
<switch_block fs="3" type="universal"/>
117+
<chan_width_distr>
118+
<x distr="uniform" peak="1.0"/>
119+
<y distr="uniform" peak="1.0"/>
120+
</chan_width_distr>
121+
</device>
122+
<switchlist>
123+
<switch Cin=".77e-15" Cout="4e-15" R="1" Tdel="58e-12" buf_size="27.645901" mux_trans_size="2.630740" name="sw" type="mux"/>
124+
</switchlist>
125+
<segmentlist>
126+
<segment Cmetal="22.5e-15" Rmetal="101" freq="1.0" name="wire" type="bidir" length="1">
127+
<wire_switch name="sw"/>
128+
<opin_switch name="sw"/>
129+
<sb type="pattern">1 1</sb>
130+
<cb type="pattern">1</cb>
131+
</segment>
132+
</segmentlist>
133+
<directlist>
134+
<direct from_pin="IO_TILE_WITH_PRIMITIVE.ipad_out_rx_n" to_pin="IO_TILE_WITH_PRIMITIVE.primitive_in" x_offset="0" y_offset="0" z_offset="-1" name="IPAD_rx_n_to_PRIMITIVE"/>
135+
<direct from_pin="IO_TILE_WITH_PRIMITIVE.ipad_out_rx_p" to_pin="IO_TILE_WITH_PRIMITIVE.primitive_in_2" x_offset="0" y_offset="0" z_offset="-2" name="IPAD_rx_p_to_PRIMITIVE"/>
136+
<direct from_pin="IO_TILE_WITH_PRIMITIVE.primitive_out" to_pin="IO_TILE_WITH_PRIMITIVE.opad_in_tx_n" x_offset="0" y_offset="0" z_offset="3" name="PRIMITIVE_to_OPAD_tx_n"/>
137+
<direct from_pin="IO_TILE_WITH_PRIMITIVE.primitive_out_2" to_pin="IO_TILE_WITH_PRIMITIVE.opad_in_tx_p" x_offset="0" y_offset="0" z_offset="4" name="PRIMITIVE_to_OPAD_tx_p"/>
138+
</directlist>
139+
</architecture>

‎vtr_flow/benchmarks/microbenchmarks/sub_tile_directs.blif

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
.model top
2+
.inputs in_0 in_1
3+
.outputs out_0 out_1
4+
.names $false
5+
.names $true
6+
1
7+
.subckt PRIMITIVE in=in_0 in_2=in_1 out=out_0 out_2=out_1
8+
.end

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/config.txt

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
##############################################
2+
# Configuration file for running experiments
3+
##############################################
4+
5+
# Path to directory of circuits to use
6+
circuits_dir=benchmarks/microbenchmarks
7+
8+
# Path to directory of architectures to use
9+
archs_dir=arch/sub_tiles
10+
11+
# Add circuits to list to sweep
12+
circuit_list_add=sub_tile_directs.blif
13+
14+
# Add architectures to list to sweep
15+
arch_list_add=heterogeneous_tile.xml
16+
17+
# Parse info and how to parse
18+
parse_file=vpr_standard.txt
19+
20+
# How to parse QoR info
21+
qor_parse_file=qor_standard.txt
22+
23+
# Pass requirements
24+
pass_requirements_file=pass_requirements.txt
25+
26+
# Script parameters
27+
script_params=-track_memory_usage -lut_size 1 -starting_stage vpr

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+
heterogeneous_tile.xml sub_tile_directs.blif common 0.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-3379-gb880e9773 debug VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-101-generic x86_64 2021-03-01T13:49:39 acomodi /data/tmp/vtr/vtr_flow/tasks 60172 2 2 4 5 0 4 5 3 3 9 -1 auto 0.00 8 0.01 0.00 2.02889 -4.05778 -2.02889 nan 0.32 0.000167349 0.000130577 0.00549792 0.0015696 1 0 1 0 0 -1 -1 0.15 0.0101232 0.00513767 0 1 4 4 24 16 1.667 nan -3.334 -1.667 0 0 -1 -1 0.00 0.01 0.00301969 0.0022951

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,7 @@ regression_tests/vtr_reg_strong/strong_graphics_commands
6565
regression_tests/vtr_reg_strong/strong_clock_pll
6666
regression_tests/vtr_reg_strong/strong_place_effort_scaling
6767
regression_tests/vtr_reg_strong/strong_sub_tiles
68+
regression_tests/vtr_reg_strong/strong_sub_tiles_directs
6869
regression_tests/vtr_reg_strong/strong_check_route_options
6970
regression_tests/vtr_reg_strong/strong_pack_disable
7071
regression_tests/vtr_reg_strong/strong_timing_update_type

0 commit comments

Comments
 (0)