Merge branch 'master' into ingest_per_edge_delay

Author: soheilshahrouz

.clang-format

@@ -15,7 +15,7 @@ AllowShortIfStatementsOnASingleLine: true
 AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: true
+AlwaysBreakBeforeMultilineStrings: false
 AlwaysBreakTemplateDeclarations: true
 BinPackArguments: true
 BinPackParameters: false
@@ -34,7 +34,7 @@ BraceWrapping:
   SplitEmptyFunction: false
   SplitEmptyRecord: true
   SplitEmptyNamespace: true
-BreakBeforeBinaryOperators: All
+BreakBeforeBinaryOperators: NonAssignment
 BreakBeforeBraces: Custom
 BreakBeforeInheritanceComma: false
 BreakBeforeTernaryOperators: true
@@ -68,10 +68,10 @@ IncludeIsMainRegex: '([-_](test|unittest))?$'
 IndentCaseLabels: true
 IndentWidth:     4
 IndentWrappedFunctionNames: false
-IndentPPDirectives: AfterHash
+IndentPPDirectives: None
 JavaScriptQuotes: Leave
 JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
+KeepEmptyLinesAtTheStartOfBlocks: true
 MacroBlockBegin: ''
 MacroBlockEnd:   ''
 MaxEmptyLinesToKeep: 1

.github/scripts/install_dependencies.sh

@@ -55,7 +55,7 @@ sudo apt install -y \
   clang-16 \
   clang-17 \
   clang-18 \
-  clang-format-14 \
+  clang-format-18 \
   libtbb-dev
 
 pip install -r requirements.txt

.github/workflows/test.yml

@@ -89,6 +89,8 @@ jobs:
       with:
         python-version: 3.10.10
     - uses: actions/checkout@v4
+      with:
+        submodules: 'true'
 
     - name: Install dependencies
       run: ./.github/scripts/install_dependencies.sh

cmake/modules/AutoClangFormat.cmake

@@ -21,11 +21,11 @@ add_custom_target(format-cpp-files
     COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP})
 
 #
-# Use clang-format-14 for code format
+# Use clang-format for code format
 #
 add_custom_target(format-cpp
     COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP} |
-    xargs -P ${CPU_COUNT} clang-format-14 -style=file -i)
+    xargs -P ${CPU_COUNT} clang-format-18 -style=file -i)
 
 #
 # Use simple python script for fixing C like boxed comments

dev/pylint_check.py

@@ -132,7 +132,7 @@ def expand_paths():
     """Build a list of all python files to process by going through 'paths_to_lint'"""
 
     paths = []
-    for (path, is_recursive) in paths_to_lint:
+    for path, is_recursive in paths_to_lint:
         # Make sure all hard-coded paths point to .py files
         if path.is_file():
             if path.suffix.lower() != ".py":

dev/submit_slurm.py

@@ -188,7 +188,7 @@ def get_resource_estimates(filepath):
                 mem_bytes = float(match.groupdict()["mem_bytes"])
 
     time_minutes = time_sec / 60
-    mem_mb = mem_bytes / (1024 ** 2)
+    mem_mb = mem_bytes / (1024**2)
 
     return time_minutes, mem_mb
 

dev/vtr_gdb_pretty_printers.py

@@ -7,8 +7,10 @@
 
     https://docs.verilogtorouting.org/en/latest/dev/developing#vtr-pretty-printers
 """
+
 import re
 
+
 # VTR related
 class VtrStrongIdPrinter:
     def __init__(self, val, typename="vtr::StrongId"):

doc/src/vpr/command_line_usage.rst

@@ -926,6 +926,13 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
 
     **Default:** ``move_block_type``
 
+.. option:: --place_quench_only {on | off}
+    
+    If this option is set to ``on``, the placement will skip the annealing phase and only perform the placement quench.
+    This option is useful when the the quality of initial placement is good enough and there is no need to perform the 
+    annealing phase.
+
+    **Default:** ``off``
 
 
 .. option:: --placer_debug_block <int>
@@ -1188,15 +1195,43 @@ Analytical Placement is generally split into three stages:
 
     Analytical Placement is experimental and under active development.
 
-.. option:: --ap_global_placer {quadratic-bipartitioning-lookahead | quadratic-flowbased-lookahead}
+.. option:: --ap_analytical_solver {qp-hybrid | lp-b2b}
+
+    Controls which Analytical Solver the Global Placer will use in the AP Flow.
+    The Analytical Solver solves for a placement which optimizes some objective
+    function, ignorant of the FPGA legality constraints. This provides a "lower-
+    bound" solution. The Global Placer will legalize this solution and feed it
+    back to the analytical solver to make its solution more legal.
+
+    * ``qp-hybrid`` Solves for a placement that minimizes the quadratic HPWL of
+      the flat placement using a hybrid clique/star net model (as described in
+      FastPlace :cite:`Viswanathan2005_FastPlace`).
+      Uses the legalized solution as anchor-points to pull the solution to a
+      more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`).
+
+    * ``lp-b2b`` Solves for a placement that minimizes the linear HPWL of the
+      flat placement using the Bound2Bound net model (as described in Kraftwerk2 :cite:`Spindler2008_Kraftwerk2`).
+      Uses the legalized solution as anchor-points to pull the solution to a
+      more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`).
+
+    **Default:** ``qp-hybrid``
+
+.. option:: --ap_partial_legalizer {bipartitioning | flow-based}
 
-    Controls which Global Placer to use in the AP Flow.
+    Controls which Partial Legalizer the Global Placer will use in the AP Flow.
+    The Partial Legalizer legalizes a placement generated by an Analytical Solver.
+    It is used within the Global Placer to guide the solver to a more legal
+    solution.
 
-    * ``quadratic-bipartitioning-lookahead`` Use a Global Placer which uses a quadratic solver and a bi-partitioning lookahead legalizer. Anchor points are used to spread the solved solution to the legalized solution.
+    * ``bipartitioning`` Creates minimum windows around over-dense regions of
+      the device bi-partitions the atoms in these windows such that the region
+      is no longer over-dense and the atoms are in tiles that they can be placed
+      into.
 
-    * ``quadratic-flowbased-lookahead`` Use a Global Placer which uses a quadratic solver and a multi-commodity-flow-based lookahead legalizer. Anchor points are used to spread the solved solution to the legalized solution.
+    * ``flow-based`` Flows atoms from regions that are overfilled to regions that
+      are underfilled.
 
-    **Default:** ``quadratic-bipartitioning-lookahead``
+    **Default:** ``bipartitioning``
 
 .. option:: --ap_full_legalizer {naive | appack}
 

doc/src/vpr/placement_constraints.rst

@@ -18,7 +18,7 @@ A Placement Constraints File Example
 		<partition_list>
 			<partition name="Part0">
 					<add_atom name_pattern="li354"/>
-					<add_atom name_pattern="alu*"/> <!-- Regular expressions can be used to provide name patterns of the primitives to be added -->
+					<add_atom name_pattern="alu.*"/> <!-- Regular expressions can be used to provide name patterns of the primitives to be added -->
 					<add_atom name_pattern="n877"/>
 					<add_region x_low="3" y_low="1" x_high="7" y_high="2"/> <!-- Two rectangular regions are specified, together describing an L-shaped region -->
 					<add_region x_low="7" y_low="3" x_high="7" y_high="6"/>
@@ -78,7 +78,10 @@ An ``<add_atom>`` tag is used to add an atom that must be constrained to the par
 :req_param name_pattern:
    The name of the atom.
 
-The ``name_pattern`` can be the exact name of the atom from the input atom netlist that was passed to VPR. It can also be a regular expression, in which case VPR will add all atoms from the netlist which have a portion of their name matching the regular expression to the partition. For example, if a module contains primitives named in the pattern of "alu[0]", "alu[1]", and "alu[2]", the regular expression "alu*" would add all of the primitives from that module.
+The ``name_pattern`` can either be the exact name of an atom from the input atom netlist passed to VPR, or a regular expression pattern matching one or more atom names. VPR first searches the netlist for an exact match. If no exact match is found, it then assumes that the given name is a regex pattern and searches for atoms whose names match the pattern.
+
+For example, to add all atoms ``alu[0]``, ``alu[1]``, and ``alu[2]`` to the partition ``Part0``, the user can use ``alu.*`` as the ``name_pattern`` in the ``<add_atom>`` tag.
+
 
 Region
 ^^^^^^
@@ -124,12 +127,3 @@ It is strongly recommended that different partitions do not overlap. The packing
 blocks and the number of physical blocks in a region to decide pack atoms inside a partition more aggressively when
 there are not enough resources in a partition. Overlapping partitions causes some physical blocks to be counted in more
 than one partition.
-
-
-
-
-
-
-
-
-

doc/src/z_references.bib

@@ -436,3 +436,46 @@ @inproceedings{kosar2024parallel
   booktitle={The 23rd International Conference on Field-Programmable Technology},
   year={2024}
 }
+
+@ARTICLE{Viswanathan2005_FastPlace,
+    author={Viswanathan, N. and Chu, C.C.-N.},
+    journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+    title={{FastPlace}: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model},
+    year={2005},
+    volume={24},
+    number={5},
+    month=may,
+    pages={722-733},
+    keywords={Clustering algorithms;Partitioning algorithms;Algorithm design and analysis;Integrated circuit interconnections;Large-scale systems;Minimization;Delay;Simulated annealing;Iterative algorithms;Acceleration;Analytical placement;computer-aided design;net models;standard cell placement},
+    doi={10.1109/TCAD.2005.846365}
+}
+
+@article{Kim2013_SimPL,
+    author = {Kim, Myung-Chul and Lee, Dong-Jin and Markov, Igor L.},
+    journal = {Commun. ACM},
+    title = {{SimPL}: an algorithm for placing {VLSI} circuits},
+    year = {2013},
+    issue_date = {June 2013},
+    publisher = {Association for Computing Machinery},
+    address = {New York, NY, USA},
+    volume = {56},
+    number = {6},
+    issn = {0001-0782},
+    doi = {10.1145/2461256.2461279},
+    month = jun,
+    pages = {105–113},
+    numpages = {9}
+}
+
+@ARTICLE{Spindler2008_Kraftwerk2,
+    author={Spindler, Peter and Schlichtmann, Ulf and Johannes, Frank M.},
+    journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+    title={Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model},
+    year={2008},
+    volume={27},
+    number={8},
+    month=aug,
+    pages={1398-1411},
+    keywords={Cost function;Central Processing Unit;Runtime;Quality control;Convergence;Computational efficiency;Integrated circuit synthesis;Stochastic processes;Circuit simulation;Bound2Bound;force-directed;half-perimeter wirelength (HPWL);Kraftwerk2;quadratic placement;Kraftwerk2;force-directed;quadratic placement;Bound2Bound;HPWL},
+    doi={10.1109/TCAD.2008.925783}
+}

libs/libarchfpga/src/device_grid.h

@@ -19,7 +19,6 @@ struct t_grid_tile {
     const t_metadata_dict* meta = nullptr;
 };
 
-
 //TODO: All of the functions that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually.
 /**
  * @class DeviceGrid

libs/libarchfpga/src/echo_arch.cpp

@@ -297,7 +297,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
                 int num_layers = (int)layout.layers.size();
                 if (num_layers > 1) {
                     fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
-                            arch->switches[seg.arch_opin_between_dice_switch].name.c_str());
+                            arch->switches[seg.arch_inter_die_switch].name.c_str());
                 }
             }
         } else { //Should be bidir