Merge branch 'master' into fixed_channel_parse_fix

Author: AmirhosseinPoolad

libs/libarchfpga/src/logic_types.h

@@ -62,10 +62,8 @@ struct t_model {
     bool never_prune = false;               ///< Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist
 };
 
-// Tag for the logical model ID
-struct logical_model_id_tag;
 // A unique ID that represents a logical model in the architecture.
-typedef vtr::StrongId<logical_model_id_tag, size_t> LogicalModelId;
+typedef vtr::StrongId<struct logical_model_id_tag, size_t> LogicalModelId;
 
 /**
  * @brief A storage class containing all of the logical models in an FPGA

libs/librrgraph/src/base/rr_graph_fwd.h

@@ -15,16 +15,9 @@ class t_rr_graph_storage;
 
 class RRGraph;
 
-struct rr_node_id_tag;
-struct rr_edge_id_tag;
-struct rr_indexed_data_id_tag;
-struct rr_switch_id_tag;
-struct rr_segment_id_tag;
-struct rc_index_tag;
-
-typedef vtr::StrongId<rr_node_id_tag, uint32_t> RRNodeId;
-typedef vtr::StrongId<rr_edge_id_tag, uint32_t> RREdgeId;
-typedef vtr::StrongId<rr_indexed_data_id_tag, uint32_t> RRIndexedDataId;
-typedef vtr::StrongId<rr_switch_id_tag, uint16_t> RRSwitchId;
-typedef vtr::StrongId<rr_segment_id_tag, uint16_t> RRSegmentId;
-typedef vtr::StrongId<rc_index_tag, uint16_t> NodeRCIndex;
+typedef vtr::StrongId<struct rr_node_id_tag, uint32_t> RRNodeId;
+typedef vtr::StrongId<struct rr_edge_id_tag, uint32_t> RREdgeId;
+typedef vtr::StrongId<struct rr_indexed_data_id_tag, uint32_t> RRIndexedDataId;
+typedef vtr::StrongId<struct rr_switch_id_tag, uint16_t> RRSwitchId;
+typedef vtr::StrongId<struct rr_segment_id_tag, uint16_t> RRSegmentId;
+typedef vtr::StrongId<struct rc_index_tag, uint16_t> NodeRCIndex;

libs/libvtrutil/test/test_vector.cpp

@@ -5,8 +5,7 @@
 
 #include <ostream>
 
-struct test_tag;
-typedef vtr::StrongId<test_tag> TestId;
+typedef vtr::StrongId<struct test_tag> TestId;
 
 std::ostream& operator<<(std::ostream& os, const TestId id);
 

vpr/src/analytical_place/analytical_solver.h

@@ -39,8 +39,7 @@ class PreClusterTimingManager;
  * This gives a linearized ID for each of the moveable blocks from 0 to the
  * number of moveable blocks.
  */
-struct ap_row_id_tag {};
-typedef vtr::StrongId<ap_row_id_tag, size_t> APRowId;
+typedef vtr::StrongId<struct ap_row_id_tag, size_t> APRowId;
 
 /**
  * @brief The Analytical Solver base class

vpr/src/analytical_place/flat_placement_bins.h

@@ -19,13 +19,10 @@
 #include "vtr_vector.h"
 #include "vtr_vector_map.h"
 
-// The tag for the flat placement bin.
-struct flat_placement_bin_tag {};
-
 /**
  * @brief A unique ID to a flat placement bin.
  */
-typedef vtr::StrongId<flat_placement_bin_tag, size_t> FlatPlacementBinId;
+typedef vtr::StrongId<struct flat_placement_bin_tag, size_t> FlatPlacementBinId;
 
 /**
  * @brief A container of bins which hold AP blocks and take up space on the FPGA.

vpr/src/analytical_place/full_legalizer.cpp

@@ -98,8 +98,7 @@ namespace {
 /// This is used for putting the molecules in bins for packing.
 // FIXME: Bring this into the device_grid.
 //  - Maybe this can be called DeviceRootTileId or something.
-struct device_tile_id_tag {};
-typedef vtr::StrongId<device_tile_id_tag, size_t> DeviceTileId;
+typedef vtr::StrongId<struct device_tile_id_tag, size_t> DeviceTileId;
 
 /**
  * @brief Helper class to place cluster in the AP context.

vpr/src/analytical_place/global_placer.cpp

@@ -127,7 +127,8 @@ static void print_placement_stats(const PartialPlacement& p_placement,
                                   FlatPlacementDensityManager& density_manager,
                                   const PreClusterTimingManager& pre_cluster_timing_manager) {
     // Print the placement HPWL
-    VTR_LOG("\tPlacement HPWL: %f\n", p_placement.get_hpwl(ap_netlist));
+    VTR_LOG("\tPlacement objective HPWL: %f\n", p_placement.get_hpwl(ap_netlist));
+    VTR_LOG("\tPlacement estimated wirelength: %u\n", p_placement.estimate_post_placement_wirelength(ap_netlist));
 
     // Print the timing information.
     if (pre_cluster_timing_manager.is_valid()) {

vpr/src/analytical_place/model_grouper.h

@@ -18,11 +18,8 @@
 // Forward declarations.
 class Prepacker;
 
-/// @brief Tag for the ModelGroupId
-struct model_group_id_tag;
-
 /// @brief A unique ID of a group of models created by the ModelGrouper class.
-typedef vtr::StrongId<model_group_id_tag, size_t> ModelGroupId;
+typedef vtr::StrongId<struct model_group_id_tag, size_t> ModelGroupId;
 
 /**
  * @brief A manager class for grouping together models that must be legalized

vpr/src/analytical_place/partial_legalizer.h

@@ -340,11 +340,8 @@ class PerPrimitiveDimPrefixSum2D {
     vtr::vector<PrimitiveVectorDim, vtr::PrefixSum2D<float>> dim_prefix_sum_;
 };
 
-/// @brief Tag for the PrimitiveGroupId
-struct primitive_group_id_tag;
-
 /// @brief A unique ID of a group of primitive dims created by the PrimitiveDimGrouper class.
-typedef vtr::StrongId<primitive_group_id_tag, size_t> PrimitiveGroupId;
+typedef vtr::StrongId<struct primitive_group_id_tag, size_t> PrimitiveGroupId;
 
 /**
  * @brief A manager class for grouping together dimensions of the primitive

vpr/src/analytical_place/partial_placement.cpp

@@ -33,6 +33,48 @@ double PartialPlacement::get_hpwl(const APNetlist& netlist) const {
     return hpwl;
 }
 
+double PartialPlacement::estimate_post_placement_wirelength(const APNetlist& netlist) const {
+    // Go through each net and calculate the half-perimeter wirelength. Since
+    // we want to estimate the post-placement wirelength, we do not want the
+    // flat placement positions of the blocks. Instead we compute the HPWL over
+    // the tiles that the flat placement is placing the blocks over.
+    unsigned total_hpwl = 0;
+    for (APNetId net_id : netlist.nets()) {
+        // Note: Other wirelength estimates in VTR ignore global nets; however
+        //       it is not known if a net is global or not until packing is
+        //       complete. For now, we just approximate post-placement wirelength
+        //       using the HPWL (in tile space).
+        // TODO: The reason we do not know what nets are ignored / global is
+        //       because the pin on the tile that the net connects to is what
+        //       decides if a net is global / ignored for place and route. Since
+        //       we have not packed anything yet, we do not know what pin each
+        //       net will go to; however, we can probably get a good idea based
+        //       on some properties of the net and the tile its going to / from.
+        //       Should investigate this to get a better estimate of wirelength.
+        double min_x = std::numeric_limits<unsigned>::max();
+        double max_x = std::numeric_limits<unsigned>::lowest();
+        double min_y = std::numeric_limits<unsigned>::max();
+        double max_y = std::numeric_limits<unsigned>::lowest();
+        for (APPinId pin_id : netlist.net_pins(net_id)) {
+            APBlockId blk_id = netlist.pin_block(pin_id);
+            min_x = std::min(min_x, block_x_locs[blk_id]);
+            max_x = std::max(max_x, block_x_locs[blk_id]);
+            min_y = std::min(min_y, block_y_locs[blk_id]);
+            max_y = std::max(max_y, block_y_locs[blk_id]);
+        }
+        VTR_ASSERT_SAFE(max_x >= min_x && max_y >= min_y);
+
+        // Floor the positions to get the x and y coordinates of the tiles each
+        // block belongs to.
+        unsigned tile_dx = std::floor(max_x) - std::floor(min_x);
+        unsigned tile_dy = std::floor(max_y) - std::floor(min_y);
+
+        total_hpwl += tile_dx + tile_dy;
+    }
+
+    return total_hpwl;
+}
+
 bool PartialPlacement::verify_locs(const APNetlist& netlist,
                                    size_t grid_width,
                                    size_t grid_height) const {

vpr/src/analytical_place/partial_placement.h

@@ -145,6 +145,15 @@ struct PartialPlacement {
      */
     double get_hpwl(const APNetlist& netlist) const;
 
+    /**
+     * @brief Estimate the wirelength of the current placement assuming that all
+     *        blocks will be placed exactly where they are in the partial placement.
+     *
+     * NOTE: This is an underestimate of the actual wirelength mainly due to
+     *       the placement not being legalized yet.
+     */
+    double estimate_post_placement_wirelength(const APNetlist& netlist) const;
+
     /**
      * @brief Verify the block_x_locs and block_y_locs vectors
      *

vpr/src/analytical_place/primitive_vector_fwd.h

@@ -9,11 +9,8 @@
 #include <cstddef>
 #include "vtr_strong_id.h"
 
-/// @brief Tag for the PrimitiveVectorDim
-struct primitive_vector_dim_tag;
-
 /// @brief A unique dimension in the PrimtiveVector class.
-typedef vtr::StrongId<primitive_vector_dim_tag, size_t> PrimitiveVectorDim;
+typedef vtr::StrongId<struct primitive_vector_dim_tag, size_t> PrimitiveVectorDim;
 
 // Forward declaration of the Primitive Vector class.
 class PrimitiveVector;

vpr/src/base/netlist.h

@@ -939,10 +939,8 @@ class Netlist {
     NetId add_net(const std::string name, PinId driver, std::vector<PinId> sinks);
 
   protected: //Protected Base Types
-    struct string_id_tag;
-
     ///@brief A unique identifier for a string in the netlist
-    typedef vtr::StrongId<string_id_tag> StringId;
+    typedef vtr::StrongId<struct string_id_tag> StringId;
 
   protected: //Protected Base Members
     /*

vpr/src/base/netlist_fwd.h

@@ -15,16 +15,16 @@ struct general_pin_id_tag {};
 struct general_net_id_tag {};
 
 //A unique identifier for a block/primitive in the atom netlist
-typedef vtr::StrongId<general_blk_id_tag> ParentBlockId;
+typedef vtr::StrongId<struct general_blk_id_tag> ParentBlockId;
 
 //A unique identifier for a net in the atom netlist
-typedef vtr::StrongId<general_port_id_tag> ParentPortId;
+typedef vtr::StrongId<struct general_port_id_tag> ParentPortId;
 
 //A unique identifier for a port in the atom netlist
-typedef vtr::StrongId<general_pin_id_tag> ParentPinId;
+typedef vtr::StrongId<struct general_pin_id_tag> ParentPinId;
 
 //A unique identifier for a pin in the atom netlist
-typedef vtr::StrongId<general_net_id_tag> ParentNetId;
+typedef vtr::StrongId<struct general_net_id_tag> ParentNetId;
 
 template<typename BlockId, typename PortId, typename PinId, typename NetId>
 class Netlist;

vpr/src/base/partition.h

@@ -15,11 +15,8 @@
  * with L, T or other shapes can be created with a union of multiple rectangles.
  */
 
-/// @brief Type tag for PartitionId
-struct partition_id_tag;
-
 /// @brief A unique identifier for a partition
-typedef vtr::StrongId<partition_id_tag> PartitionId;
+typedef vtr::StrongId<struct partition_id_tag> PartitionId;
 
 class Partition {
   public:

vpr/src/noc/noc_data_types.h

@@ -8,20 +8,16 @@
 #include "vtr_strong_id.h"
 
 // data types used to index the routers and links within the noc
-struct noc_router_id_tag;
-struct noc_link_id_tag;
 
 /** Datatype to index routers within the NoC */
-typedef vtr::StrongId<noc_router_id_tag, int> NocRouterId;
+typedef vtr::StrongId<struct noc_router_id_tag, int> NocRouterId;
 /** Datatype to index links within the NoC */
-typedef vtr::StrongId<noc_link_id_tag, int> NocLinkId;
+typedef vtr::StrongId<struct noc_link_id_tag, int> NocLinkId;
 
 // data type to index traffic flows within the noc
-struct noc_traffic_flow_id_tag;
 
 /** Datatype to index traffic flows within the application */
-typedef vtr::StrongId<noc_traffic_flow_id_tag, int> NocTrafficFlowId;
+typedef vtr::StrongId<struct noc_traffic_flow_id_tag, int> NocTrafficFlowId;
 
 /** Data type to index NoC groups. */
-struct noc_group_id_tag;
-typedef vtr::StrongId<noc_group_id_tag, int> NocGroupId;
+typedef vtr::StrongId<struct noc_group_id_tag, int> NocGroupId;

vpr/src/pack/cluster_legalizer.h

@@ -34,8 +34,7 @@ struct t_lb_router_data;
 // A special ID to identify the legalization clusters. This is separate from the
 // ClusterBlockId since this legalizer is not necessarily tied to the Clustered
 // netlist, but is used as a sub-routine to it.
-struct legalization_cluster_id_tag;
-typedef vtr::StrongId<legalization_cluster_id_tag, size_t> LegalizationClusterId;
+typedef vtr::StrongId<struct legalization_cluster_id_tag, size_t> LegalizationClusterId;
 
 /**
  * @brief Holds information to be shared between molecules that represent the

vpr/src/pack/prepack.h

@@ -23,12 +23,10 @@ class LogicalModels;
 struct t_logical_block_type;
 
 // A unique ID used to identify a molecule generated by the prepacker.
-struct pack_molecule_id_tag;
-typedef vtr::StrongId<pack_molecule_id_tag, size_t> PackMoleculeId;
+typedef vtr::StrongId<struct pack_molecule_id_tag, size_t> PackMoleculeId;
 
 // A unique ID used to identify a chain of molecules generated by the prepacker.
-struct molecule_chain_id_tag;
-typedef vtr::StrongId<molecule_chain_id_tag, size_t> MoleculeChainId;
+typedef vtr::StrongId<struct molecule_chain_id_tag, size_t> MoleculeChainId;
 
 /**
  * @brief Holds general information to be shared between molecules that

vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt

@@ -2,7 +2,7 @@
 # channel width.
 
 vpr_status;output.txt;vpr_status=(.*)
-post_gp_hpwl;vpr.out;\s*Placement HPWL: (.*)
+post_gp_hpwl;vpr.out;\s*Placement estimated wirelength: (.*)
 post_fl_hpwl;vpr.out;Initial placement BB estimate of wirelength: (.*)
 post_dp_hpwl;vpr.out;BB estimate of min-dist \(placement\) wire length: (.*)
 total_wirelength;vpr.out;\s*Total wirelength: (\d+)

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt

@@ -1,2 +1,2 @@
  arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  initial_placed_wirelength_est	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  initial_placed_CPD_est	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- 7series_BRAM_DSP_carry.xml	  stereovision3.v	  common	  4.67	  vpr	  71.88 MiB	  	  -1	  -1	  0.35	  24184	  5	  0.11	  -1	  -1	  32616	  -1	  -1	  -1	  11	  0	  -1	  success	  v8.0.0-13078-g2957e2731	  release IPO VTR_ASSERT_LEVEL=2	  GNU 13.3.0 on Linux-6.8.0-60-generic x86_64	  2025-06-16T18:49:38	  betzgrp-wintermute	  /home/pooladam/vtr-verilog-to-routing	  73604	  11	  2	  303	  283	  2	  114	  35	  7	  7	  49	  CLB	  auto	  32.5 MiB	  1.56	  569.025	  404	  890	  113	  545	  232	  71.9 MiB	  0.02	  0.00	  3.1717	  3.1717	  -181.811	  -3.1717	  2.89952	  0.16	  0.000410323	  0.000358804	  0.00972892	  0.00889236	  -1	  -1	  -1	  -1	  44	  515	  16	  1.34735e+06	  1.18567e+06	  177202.	  3616.36	  1.30	  0.156453	  0.134936	  6848	  92556	  -1	  373	  9	  263	  823	  105258	  48434	  2.83816	  2.83244	  -218.271	  -2.83816	  -2.452	  -0.04	  257836.	  5261.96	  0.04	  0.03	  0.08	  -1	  -1	  0.04	  0.017287	  0.0159941	 
+ 7series_BRAM_DSP_carry.xml	  stereovision3.v	  common	  5.34	  vpr	  74.72 MiB	  	  -1	  -1	  0.36	  34424	  5	  0.10	  -1	  -1	  36444	  -1	  -1	  -1	  11	  0	  -1	  success	  v8.0.0-13075-g071b36c3f	  release VTR_ASSERT_LEVEL=3	  GNU 13.3.0 on Linux-6.8.0-58-generic x86_64	  2025-06-16T21:07:45	  srivatsan-Precision-Tower-5810	  /home/alex/vtr-verilog-to-routing	  76512	  11	  2	  303	  283	  2	  114	  35	  7	  7	  49	  CLB	  auto	  35.3 MiB	  1.64	  569.025	  404	  890	  113	  545	  232	  74.7 MiB	  0.02	  0.00	  3.1717	  3.1717	  -181.811	  -3.1717	  2.89952	  0.27	  0.00043783	  0.000361293	  0.0101279	  0.00875535	  -1	  -1	  -1	  -1	  44	  529	  20	  1.34735e+06	  1.18567e+06	  177202.	  3616.36	  1.77	  0.144934	  0.119762	  6848	  92556	  -1	  373	  9	  263	  823	  105258	  48434	  2.83816	  2.83244	  -218.271	  -2.83816	  -2.452	  -0.04	  257836.	  5261.96	  0.06	  0.03	  0.13	  -1	  -1	  0.06	  0.0166581	  0.0151597