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odin - free leaks from hard blocks, add new tests
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‎ODIN_II/SRC/netlist_create_from_ast.cpp

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Original file line numberDiff line numberDiff line change
@@ -5832,6 +5832,8 @@ signal_list_t *create_hard_block(ast_node_t* block, char *instance_name_prefix,
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/* add the net to the list of inputs */
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sc_spot = sc_add_string(input_nets_sc, pin_name);
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input_nets_sc->data[sc_spot] = (void*)new_net;
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vtr::free(pin_name);
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}
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current_out_idx += j;
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}
@@ -5890,6 +5892,8 @@ signal_list_t *create_hard_block(ast_node_t* block, char *instance_name_prefix,
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/* add the net to the list of inputs */
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sc_spot = sc_add_string(input_nets_sc, pin_name);
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input_nets_sc->data[sc_spot] = (void*)new_net;
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vtr::free(pin_name);
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}
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current_out_idx += j;
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}

‎ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf

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@@ -2,6 +2,7 @@ regression_test/benchmark/task/arch_sweep
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regression_test/benchmark/task/rs_decoder
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regression_test/benchmark/task/cmd_line_args/*
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regression_test/benchmark/task/func_simulator/*
5+
regression_test/benchmark/task/hard_blocks
56
regression_test/benchmark/task/multiclock/*
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regression_test/benchmark/task/operators
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regression_test/benchmark/task/syntax

‎ODIN_II/regression_test/benchmark/task/hard_blocks/task.conf

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########################
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# hard blocks benchmarks config
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########################
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script_synthesis_params=--time_limit 3600s --tool valgrind
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script_simulation_params=--time_limit 3600s
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# setup the architecture
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arch_dir=../vtr_flow/arch/timing
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arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
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# setup the circuits
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circuit_dir=regression_test/benchmark/verilog/micro
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circuit_list_add=adder_hard_block.v
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circuit_list_add=multiply_hard_block.v

‎ODIN_II/regression_test/benchmark/task/micro/task.conf

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@@ -80,3 +80,8 @@ circuit_list_add=bm_if_common.v
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circuit_list_add=bm_if_collapse.v
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circuit_list_add=case_generate.v
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circuit_list_add=if_generate.v
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# these require specific architectures to run without errors
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# circuit_list_add=adder_hard_block.v
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# circuit_list_add=multiply_hard_block.v

‎ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block.v

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module top_module
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(
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input [1:0] a1, b1, a2, b2,
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input cin1, cin2,
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output [1:0] sumout1, sumout2,
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output cout1, cout2
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);
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adder a1 (.a(a1), .b(b1), .cin(cin1), .sumout(sumout1), .cout(cout1));
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adder a2 (a2, b2, cin2, sumout2, cout2);
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endmodule

‎ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_input

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@@ -0,0 +1,101 @@
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GLOBAL_SIM_BASE_CLK a1 b1 a2 b2 cin1 cin2
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1 0X2 0X3 0X1 0X2 1 0
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0 0X2 0X1 0X0 0X0 1 0
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1 0X1 0X0 0X3 0X3 0 0
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0 0X3 0X1 0X1 0X3 1 1
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1 0X1 0X2 0X2 0X2 0 0
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0 0X0 0X2 0X3 0X2 0 1
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1 0X3 0X1 0X1 0X1 1 0
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0 0X1 0X1 0X0 0X0 1 1
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1 0X1 0X0 0X2 0X0 0 0
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0 0X1 0X0 0X3 0X1 1 0
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1 0X2 0X0 0X3 0X1 1 0
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0 0X3 0X3 0X3 0X3 1 0
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1 0X1 0X1 0X3 0X0 1 0
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0 0X3 0X0 0X2 0X2 0 1
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1 0X1 0X3 0X3 0X0 0 1
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0 0X1 0X0 0X0 0X1 1 1
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1 0X3 0X0 0X3 0X2 1 0
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0 0X2 0X3 0X3 0X0 1 1
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1 0X1 0X2 0X3 0X0 0 0
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0 0X0 0X3 0X1 0X2 0 1
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1 0X1 0X1 0X2 0X1 0 1
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0 0X0 0X3 0X1 0X2 0 0
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1 0X1 0X0 0X2 0X2 1 1
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0 0X2 0X0 0X0 0X2 0 0
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1 0X0 0X1 0X0 0X0 1 1
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0 0X2 0X3 0X1 0X1 0 1
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1 0X3 0X2 0X3 0X0 1 0
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0 0X0 0X0 0X0 0X2 1 0
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1 0X2 0X0 0X2 0X1 0 0
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0 0X2 0X1 0X3 0X3 1 0
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1 0X1 0X3 0X2 0X0 0 0
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0 0X2 0X2 0X0 0X0 0 0
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1 0X1 0X1 0X0 0X1 0 0
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0 0X3 0X1 0X2 0X0 1 1
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1 0X0 0X1 0X2 0X2 1 1
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0 0X2 0X1 0X2 0X0 0 0
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1 0X1 0X0 0X1 0X0 0 0
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0 0X1 0X3 0X1 0X0 1 0
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1 0X1 0X0 0X3 0X2 1 1
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0 0X1 0X2 0X0 0X1 1 1
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1 0X0 0X1 0X0 0X1 0 0
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0 0X2 0X3 0X1 0X2 0 1
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1 0X2 0X3 0X2 0X2 1 0
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0 0X1 0X3 0X3 0X1 0 1
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1 0X3 0X0 0X3 0X2 0 0
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0 0X3 0X0 0X1 0X2 1 1
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1 0X1 0X1 0X3 0X0 0 0
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0 0X0 0X1 0X0 0X0 0 0
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1 0X0 0X1 0X2 0X2 0 1
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0 0X3 0X0 0X2 0X0 0 1
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1 0X3 0X2 0X1 0X3 0 0
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0 0X0 0X2 0X0 0X3 1 1
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1 0X2 0X3 0X2 0X3 1 1
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0 0X1 0X3 0X2 0X0 1 0
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1 0X3 0X3 0X0 0X3 1 1
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0 0X0 0X3 0X1 0X0 0 1
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1 0X3 0X1 0X3 0X3 1 1
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0 0X0 0X2 0X1 0X0 1 1
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1 0X0 0X0 0X1 0X0 1 1
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0 0X0 0X2 0X3 0X1 1 1
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1 0X0 0X0 0X3 0X1 1 1
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0 0X3 0X1 0X1 0X1 1 0
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1 0X2 0X2 0X0 0X1 1 1
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0 0X2 0X3 0X2 0X2 0 0
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1 0X1 0X3 0X3 0X3 0 1
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0 0X0 0X1 0X3 0X0 0 0
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1 0X3 0X3 0X1 0X3 0 0
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0 0X1 0X3 0X1 0X1 1 1
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1 0X3 0X0 0X1 0X2 0 0
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0 0X3 0X0 0X2 0X0 1 0
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1 0X2 0X1 0X2 0X2 0 1
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0 0X2 0X0 0X2 0X0 0 0
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1 0X0 0X3 0X2 0X0 0 0
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0 0X3 0X3 0X1 0X1 1 1
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1 0X3 0X1 0X2 0X0 0 0
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0 0X1 0X2 0X2 0X3 0 0
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1 0X2 0X1 0X2 0X3 0 0
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0 0X2 0X3 0X3 0X0 1 1
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1 0X1 0X0 0X3 0X1 1 1
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0 0X2 0X2 0X3 0X2 0 0
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1 0X3 0X0 0X1 0X3 0 1
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0 0X2 0X1 0X2 0X3 0 0
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1 0X2 0X0 0X3 0X2 0 0
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0 0X0 0X0 0X2 0X2 1 0
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1 0X0 0X3 0X0 0X1 1 0
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0 0X1 0X3 0X0 0X1 1 1
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1 0X2 0X3 0X1 0X2 0 0
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0 0X3 0X0 0X1 0X3 1 1
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1 0X0 0X3 0X1 0X0 1 0
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0 0X0 0X0 0X2 0X2 1 0
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1 0X1 0X3 0X1 0X1 1 1
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0 0X1 0X3 0X3 0X2 0 0
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1 0X0 0X0 0X2 0X1 1 1
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0 0X1 0X2 0X1 0X3 1 0
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1 0X2 0X0 0X1 0X2 1 1
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0 0X3 0X1 0X0 0X2 0 1
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1 0X0 0X3 0X1 0X2 0 0
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0 0X0 0X1 0X1 0X0 1 1
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1 0X1 0X3 0X2 0X3 1 0
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0 0X2 0X3 0X1 0X3 1 1

‎ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_output

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sumout1 sumout2 cout1 cout2
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0X1 0X3 1 0
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0X3 0X0 0 0
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0X1 0X2 0 1
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0X0 0X0 1 1
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0X3 0X0 0 1
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0X2 0X1 0 1
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0X0 0X2 1 0
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0X2 0X0 0 0
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0X1 0X2 0 0
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0X1 0X0 0 1
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0X2 0X0 0 1
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0X2 0X2 1 1
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0X2 0X3 0 0
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0X3 0X0 0 1
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0X0 0X3 1 0
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0X1 0X1 0 0
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0X3 0X1 0 1
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0X1 0X3 1 0
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0X3 0X3 0 0
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0X3 0X3 0 0
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0X2 0X3 0 0
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0X3 0X3 0 0
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0X1 0X0 0 1
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0X2 0X2 0 0
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0X1 0X0 0 0
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0X1 0X2 1 0
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0X1 0X3 1 0
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0X0 0X2 0 0
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0X2 0X3 0 0
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0X3 0X2 0 1
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0X0 0X2 1 0
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0X0 0X0 1 0
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0X2 0X1 0 0
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0X0 0X2 1 0
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0X1 0X0 0 1
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0X3 0X2 0 0
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0X1 0X1 0 0
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0X0 0X1 1 0
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0X1 0X1 0 1
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0X3 0X1 0 0
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0X1 0X1 0 0
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0X1 0X3 1 0
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0X1 0X0 1 1
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0X0 0X0 1 1
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0X3 0X1 0 1
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0X3 0X3 0 0
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0X2 0X3 0 0
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0X1 0X0 0 0
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0X1 0X0 0 1
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0X3 0X2 0 0
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0X1 0X0 1 1
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0X2 0X3 0 0
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0X1 0X1 1 1
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0X0 0X2 1 0
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0X2 0X3 1 0
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0X3 0X1 0 0
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0X0 0X2 1 1
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0X2 0X1 0 0
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0X0 0X1 0 0
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0X2 0X0 0 1
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0X0 0X0 0 1
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0X0 0X2 1 0
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0X0 0X1 1 0
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0X1 0X0 1 1
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0X0 0X2 1 1
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0X1 0X3 0 0
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0X2 0X0 1 1
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0X0 0X2 1 0
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0X3 0X3 0 0
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0X3 0X2 0 0
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0X3 0X0 0 1
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0X2 0X2 0 0
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0X3 0X2 0 0
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0X2 0X2 1 0
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0X0 0X2 1 0
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0X3 0X1 0 1
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0X3 0X1 0 1
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0X1 0X3 1 0
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0X1 0X0 0 1
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0X0 0X1 1 1
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0X3 0X0 0 1
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0X3 0X1 0 1
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0X2 0X1 0 1
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0X0 0X0 0 1
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0X3 0X1 0 0
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0X0 0X1 1 0
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0X1 0X3 1 0
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0X3 0X0 0 1
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0X3 0X1 0 0
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0X0 0X0 0 1
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0X0 0X2 1 0
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0X0 0X1 1 1
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0X0 0X3 0 0
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0X3 0X0 0 1
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0X2 0X3 0 0
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0X0 0X2 1 0
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0X3 0X3 0 0
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0X1 0X1 0 0
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0X0 0X1 1 1
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0X1 0X0 1 1

‎ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block.v

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module top_module
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(
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input [1:0] x1, x2, x3, x4,
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output [3:0] y1, y2
6+
);
7+
8+
multiply m1 (.a(x1), .b(x2), .out(y1));
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multiply m2 (x3, x4, y2);
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endmodule

‎ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_input

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GLOBAL_SIM_BASE_CLK x1 x2 x3 x4
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1 0X2 0X3 0X1 0X2
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0 0X2 0X2 0X1 0X0
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1 0X2 0X2 0X1 0X0
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0 0X3 0X1 0X0 0X3
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1 0X2 0X2 0X3 0X1
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0 0X0 0X1 0X1 0X1
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1 0X1 0X0 0X3 0X1
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0 0X2 0X2 0X3 0X2
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1 0X1 0X1 0X2 0X2
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0 0X0 0X0 0X3 0X2
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1 0X0 0X2 0X0 0X0
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0 0X1 0X0 0X3 0X1
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1 0X0 0X2 0X0 0X3
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0 0X2 0X2 0X3 0X3
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1 0X3 0X3 0X2 0X1
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0 0X2 0X1 0X2 0X2
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1 0X1 0X0 0X1 0X1
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0 0X2 0X2 0X3 0X1
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1 0X2 0X2 0X0 0X0
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0 0X1 0X3 0X3 0X1
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1 0X3 0X2 0X1 0X1
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0 0X3 0X3 0X0 0X3
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1 0X1 0X2 0X3 0X0
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0 0X0 0X0 0X3 0X1
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1 0X1 0X1 0X1 0X1
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0 0X3 0X0 0X1 0X0
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1 0X3 0X0 0X1 0X2
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0 0X0 0X0 0X1 0X3
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1 0X0 0X1 0X0 0X0
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0 0X0 0X0 0X2 0X0
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1 0X0 0X3 0X0 0X3
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0 0X1 0X1 0X2 0X3
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1 0X2 0X3 0X0 0X1
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0 0X0 0X0 0X0 0X2
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1 0X2 0X2 0X0 0X2
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0 0X0 0X2 0X2 0X1
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1 0X3 0X3 0X2 0X1
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0 0X1 0X1 0X0 0X0
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1 0X1 0X1 0X0 0X0
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0 0X3 0X2 0X0 0X2
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1 0X0 0X2 0X3 0X0
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0 0X0 0X3 0X1 0X2
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1 0X2 0X2 0X3 0X1
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0 0X1 0X2 0X0 0X0
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1 0X1 0X0 0X1 0X0
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0 0X0 0X1 0X3 0X1
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1 0X2 0X0 0X1 0X0
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0 0X1 0X3 0X3 0X1
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1 0X1 0X2 0X2 0X1
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0 0X2 0X0 0X2 0X0
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1 0X0 0X3 0X3 0X0
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0 0X2 0X1 0X3 0X1
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1 0X2 0X1 0X3 0X2
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0 0X3 0X1 0X2 0X3
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1 0X0 0X3 0X2 0X0
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0 0X3 0X0 0X1 0X2
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1 0X3 0X1 0X1 0X3
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0 0X0 0X2 0X0 0X1
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1 0X0 0X0 0X0 0X0
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0 0X0 0X1 0X1 0X3
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1 0X1 0X0 0X1 0X0
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0 0X2 0X1 0X3 0X2
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1 0X0 0X0 0X0 0X1
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0 0X3 0X3 0X1 0X3
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1 0X2 0X3 0X3 0X2
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0 0X3 0X2 0X0 0X1
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1 0X3 0X3 0X0 0X3
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0 0X3 0X0 0X3 0X1
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1 0X0 0X3 0X3 0X1
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0 0X3 0X3 0X1 0X0
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1 0X3 0X0 0X2 0X1
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0 0X0 0X2 0X0 0X2
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1 0X1 0X0 0X3 0X3
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0 0X3 0X1 0X0 0X2
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1 0X1 0X3 0X2 0X3
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0 0X1 0X1 0X1 0X0
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1 0X2 0X0 0X1 0X3
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0 0X2 0X3 0X2 0X2
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1 0X0 0X1 0X3 0X3
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0 0X1 0X3 0X0 0X1
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1 0X1 0X0 0X2 0X3
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0 0X3 0X2 0X1 0X2
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1 0X2 0X3 0X2 0X2
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0 0X2 0X1 0X2 0X0
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1 0X0 0X2 0X1 0X0
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0 0X0 0X1 0X0 0X3
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1 0X2 0X2 0X2 0X0
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0 0X0 0X2 0X0 0X0
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1 0X0 0X3 0X2 0X0
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0 0X2 0X3 0X3 0X1
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1 0X2 0X3 0X3 0X1
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0 0X1 0X0 0X0 0X1
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1 0X1 0X3 0X1 0X0
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0 0X3 0X0 0X3 0X1
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1 0X1 0X3 0X3 0X1
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0 0X3 0X2 0X0 0X2
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1 0X1 0X3 0X1 0X1
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0 0X3 0X2 0X0 0X2
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1 0X0 0X1 0X3 0X2
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0 0X2 0X1 0X2 0X3

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