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SamuelHo10SamuelHo10
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replaced t_clock_arch with std::shared_ptr<std::vector<t_clock_network>>
1 parent 2c12600 commit b697f60

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9 files changed

+115
-156
lines changed

9 files changed

+115
-156
lines changed

‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 12 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -162,10 +162,6 @@ void free_arch(t_arch* arch) {
162162

163163
vtr::free(arch->architecture_id);
164164

165-
if (arch->clocks) {
166-
delete[] arch->clocks->clock_inf;
167-
}
168-
169165
delete (arch->noc);
170166
}
171167

@@ -332,11 +328,7 @@ static void free_pb_type(t_pb_type* pb_type) {
332328
if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) {
333329
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins);
334330
}
335-
for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) {
336-
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]);
337-
}
338-
delete[] pb_type->modes[i].interconnect[j].annotations[k].prop;
339-
delete[] pb_type->modes[i].interconnect[j].annotations[k].value;
331+
340332
}
341333
delete[] pb_type->modes[i].interconnect[j].annotations;
342334
if (pb_type->modes[i].interconnect[j].interconnect_power)
@@ -351,11 +343,7 @@ static void free_pb_type(t_pb_type* pb_type) {
351343
delete[] pb_type->modes;
352344

353345
for (int i = 0; i < pb_type->num_annotations; ++i) {
354-
for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) {
355-
vtr::free(pb_type->annotations[i].value[j]);
356-
}
357-
delete[] pb_type->annotations[i].value;
358-
delete[] pb_type->annotations[i].prop;
346+
359347
if (pb_type->annotations[i].input_pins) {
360348
vtr::free(pb_type->annotations[i].input_pins);
361349
}
@@ -476,7 +464,7 @@ std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical
476464
void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
477465
char* new_name,
478466
t_pb_type* copy) {
479-
int i, j;
467+
int i;
480468
char* dot;
481469

482470
VTR_ASSERT(pb_type->blif_model != nullptr);
@@ -546,13 +534,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
546534
copy->annotations[i].line_num = pb_type->annotations[i].line_num;
547535
copy->annotations[i].format = pb_type->annotations[i].format;
548536
copy->annotations[i].type = pb_type->annotations[i].type;
549-
copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs;
550-
copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs];
551-
copy->annotations[i].value = new char*[pb_type->annotations[i].num_value_prop_pairs];
552-
for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) {
553-
copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j];
554-
copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]);
555-
}
537+
copy->annotations[i].pairs = pb_type->annotations[i].pairs;
556538
}
557539
}
558540

@@ -561,7 +543,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
561543
char* default_name;
562544
t_port* in_port;
563545
t_port* out_port;
564-
int i, j;
546+
int i;
565547

566548
if (strcmp(lut_pb_type->name, "lut") != 0) {
567549
default_name = vtr::strdup("lut");
@@ -622,13 +604,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
622604
lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num;
623605
lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format;
624606
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
625-
lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs;
626-
lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs];
627-
lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs];
628-
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
629-
lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j];
630-
lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]);
631-
}
607+
608+
lut_pb_type->modes[0].interconnect[0].annotations[i].pairs = lut_pb_type->annotations[i].pairs;
632609
}
633610

634611
/* Second mode, LUT */
@@ -643,11 +620,6 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
643620
lut_pb_type->modes[1].pb_type_children);
644621
/* moved annotations to child so delete old annotations */
645622
for (i = 0; i < lut_pb_type->num_annotations; i++) {
646-
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
647-
vtr::free(lut_pb_type->annotations[i].value[j]);
648-
}
649-
delete[] lut_pb_type->annotations[i].value;
650-
delete[] lut_pb_type->annotations[i].prop;
651623
if (lut_pb_type->annotations[i].input_pins) {
652624
vtr::free(lut_pb_type->annotations[i].input_pins);
653625
}
@@ -1099,8 +1071,8 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty
10991071
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
11001072
InstPort annot_in(annot->input_pins);
11011073
if (annot_in.port_name() == port->name) {
1102-
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
1103-
if (annot->prop[iprop] == annot_type) {
1074+
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
1075+
if (annot->pairs[iprop].first == annot_type) {
11041076
return annot;
11051077
}
11061078
}
@@ -1118,9 +1090,9 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb
11181090
for (const auto& annot_out_str : vtr::split(annot->output_pins)) {
11191091
InstPort out_pins(annot_out_str);
11201092
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
1121-
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
1122-
if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1123-
|| annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
1093+
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
1094+
if (annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1095+
|| annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
11241096
return annot;
11251097
}
11261098
}

‎libs/libarchfpga/src/echo_arch.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -335,19 +335,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
335335
fprintf(Echo, "*************************************************\n");
336336
fprintf(Echo, "Clock:\n");
337337
if (arch->clocks) {
338-
for (int i = 0; i < arch->clocks->num_global_clocks; i++) {
339-
if (arch->clocks->clock_inf[i].autosize_buffer) {
340-
fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1,
341-
arch->clocks->clock_inf->C_wire);
338+
for (size_t i = 0; i < arch->clocks->size(); i++) {
339+
if ((*arch->clocks)[i].autosize_buffer) {
340+
fprintf(Echo, "\tClock[%zu]: buffer_size auto C_wire %e", i + 1,
341+
(*arch->clocks)[i].C_wire);
342342
} else {
343-
fprintf(Echo, "\tClock[%d]: buffer_size %e C_wire %e", i + 1,
344-
arch->clocks->clock_inf[i].buffer_size,
345-
arch->clocks->clock_inf[i].C_wire);
343+
fprintf(Echo, "\tClock[%zu]: buffer_size %e C_wire %e", i + 1,
344+
(*arch->clocks)[i].buffer_size,
345+
(*arch->clocks)[i].C_wire);
346346
}
347347
fprintf(Echo, "\t\t\t\tstat_prob %f switch_density %f period %e",
348-
arch->clocks->clock_inf[i].prob,
349-
arch->clocks->clock_inf[i].dens,
350-
arch->clocks->clock_inf[i].period);
348+
(*arch->clocks)[i].prob,
349+
(*arch->clocks)[i].dens,
350+
(*arch->clocks)[i].period);
351351
}
352352
}
353353

@@ -419,7 +419,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
419419
pb_type->modes[i].interconnect[j].annotations[k].input_pins,
420420
pb_type->modes[i].interconnect[j].annotations[k].output_pins,
421421
pb_type->modes[i].interconnect[j].annotations[k].format,
422-
pb_type->modes[i].interconnect[j].annotations[k].value[0]);
422+
pb_type->modes[i].interconnect[j].annotations[k].pairs[0].second.c_str());
423423
}
424424
//Print power info for interconnects
425425
if (pb_type->modes[i].interconnect[j].interconnect_power) {
@@ -447,7 +447,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
447447
pb_type->annotations[k].input_pins,
448448
pb_type->annotations[k].output_pins,
449449
pb_type->annotations[k].format,
450-
pb_type->annotations[k].value[0]);
450+
pb_type->annotations[k].pairs[0].second.c_str());
451451
}
452452
}
453453
}

‎libs/libarchfpga/src/physical_types.h

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@
4747
#include "clock_types.h"
4848

4949
//Forward declarations
50-
struct t_clock_arch;
5150
struct t_clock_network;
5251
struct t_power_arch;
5352
struct t_interconnect_pins;
@@ -411,12 +410,6 @@ struct t_grid_def {
411410

412411
/************************* POWER ***********************************/
413412

414-
/* Global clock architecture */
415-
struct t_clock_arch {
416-
int num_global_clocks;
417-
t_clock_network* clock_inf; /* Details about each clock */
418-
};
419-
420413
/* Architecture information for a single clock */
421414
struct t_clock_network {
422415
bool autosize_buffer; /* autosize clock buffers */
@@ -426,6 +419,8 @@ struct t_clock_network {
426419
float prob; /* Static probability of net assigned to this clock */
427420
float dens; /* Switching density of net assigned to this clock */
428421
float period; /* Period of clock */
422+
423+
t_clock_network() = default;
429424
};
430425

431426
/* Power-related architecture information */
@@ -1163,6 +1158,8 @@ struct t_interconnect {
11631158

11641159
t_interconnect_power* interconnect_power = nullptr;
11651160
t_metadata_dict meta;
1161+
1162+
t_interconnect() = default;
11661163
};
11671164

11681165
/** Describes I/O and clock ports
@@ -1252,10 +1249,9 @@ struct t_mode_power {
12521249
* output_pins: output pins as string affected by annotation
12531250
* clock_pin: clock as string affected by annotation
12541251
*/
1255-
struct t_pin_to_pin_annotation {
1256-
char** value; /* [0..num_value_prop_pairs - 1] */
1257-
int* prop; /* [0..num_value_prop_pairs - 1] */
1258-
int num_value_prop_pairs;
1252+
struct t_pin_to_pin_annotation{
1253+
1254+
std::vector<std::pair<int, std::string>> pairs;
12591255

12601256
enum e_pin_to_pin_annotation_type type;
12611257
enum e_pin_to_pin_annotation_format format;
@@ -1265,6 +1261,8 @@ struct t_pin_to_pin_annotation {
12651261
char* clock;
12661262

12671263
int line_num; /* used to report what line number this annotation is found in architecture file */
1264+
1265+
t_pin_to_pin_annotation() = default;
12681266
};
12691267

12701268
/*************************************************************************************************
@@ -2202,7 +2200,8 @@ struct t_arch {
22022200
LogicalModels models;
22032201

22042202
t_power_arch* power = nullptr;
2205-
t_clock_arch* clocks = nullptr;
2203+
2204+
std::shared_ptr<std::vector<t_clock_network>> clocks;
22062205

22072206
//determine which layers in multi-die FPGAs require to build global routing resources
22082207
std::vector<bool> layer_global_routing;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -243,16 +243,12 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
243243
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
244244
t_pin_to_pin_annotation pp;
245245

246-
pp.prop = new int();
247-
pp.value = new char*();
248-
249246
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
250247
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
251-
pp.prop[0] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME;
252-
pp.value[0] = vtr::strdup(pp_name.c_str());
248+
pp.pairs.push_back(std::make_pair(E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name));
253249
pp.input_pins = vtr::strdup(input.c_str());
254250
pp.output_pins = vtr::strdup(output.c_str());
255-
pp.num_value_prop_pairs = 1;
251+
256252
pp.clock = nullptr;
257253

258254
return pp;

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