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Regenerated test results for fixed odin_error.h
Signed-off by Alireza Azadi <[email protected]>
1 parent 0c11cd4 commit b55ce03

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15 files changed

+189
-189
lines changed

15 files changed

+189
-189
lines changed

‎ODIN_II/SRC/netlist_cleanup.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -321,6 +321,6 @@ void remove_unused_logic(netlist_t* netlist) {
321321
mark_output_dependencies(netlist);
322322
identify_unused_nodes(netlist);
323323
remove_unused_nodes(&useless_nodes);
324-
report_removed_nodes(num_removed_nodes);
324+
if (global_args.all_warnings) report_removed_nodes(num_removed_nodes);
325325
calculate_addsub_statistics(&addsub_nodes);
326326
}

‎ODIN_II/regression_test/benchmark/task/fpu/hard_logic/simulation_result.json

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
"generated_blif": "bfly_generated.blif",
66
"exit": 134,
77
"errors": [
8-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
8+
"[SIMULATION] Could not resolve memory hard block fpu_mul~0 to a valid type."
99
]
1010
},
1111
"hard_logic/bgm/hard_fpu_arch_timing": {
@@ -14,7 +14,7 @@
1414
"generated_blif": "bgm_generated.blif",
1515
"exit": 134,
1616
"errors": [
17-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~6 to a valid type."
17+
"[SIMULATION] Could not resolve memory hard block fpu_mul~6 to a valid type."
1818
]
1919
},
2020
"hard_logic/dscg/hard_fpu_arch_timing": {
@@ -23,7 +23,7 @@
2323
"generated_blif": "dscg_generated.blif",
2424
"exit": 134,
2525
"errors": [
26-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_add~0 to a valid type."
26+
"[SIMULATION] Could not resolve memory hard block fpu_add~0 to a valid type."
2727
]
2828
},
2929
"hard_logic/fir/hard_fpu_arch_timing": {
@@ -32,7 +32,7 @@
3232
"generated_blif": "fir_generated.blif",
3333
"exit": 134,
3434
"errors": [
35-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
35+
"[SIMULATION] Could not resolve memory hard block fpu_mul~0 to a valid type."
3636
]
3737
},
3838
"hard_logic/mm3/hard_fpu_arch_timing": {
@@ -41,7 +41,7 @@
4141
"generated_blif": "mm3_generated.blif",
4242
"exit": 134,
4343
"errors": [
44-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
44+
"[SIMULATION] Could not resolve memory hard block fpu_mul~0 to a valid type."
4545
]
4646
},
4747
"hard_logic/ode/hard_fpu_arch_timing": {
@@ -50,7 +50,7 @@
5050
"generated_blif": "ode_generated.blif",
5151
"exit": 134,
5252
"errors": [
53-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
53+
"[SIMULATION] Could not resolve memory hard block fpu_mul~0 to a valid type."
5454
]
5555
},
5656
"hard_logic/syn2/hard_fpu_arch_timing": {
@@ -59,7 +59,7 @@
5959
"generated_blif": "syn2_generated.blif",
6060
"exit": 134,
6161
"errors": [
62-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~5 to a valid type."
62+
"[SIMULATION] Could not resolve memory hard block fpu_mul~5 to a valid type."
6363
]
6464
},
6565
"hard_logic/syn7/hard_fpu_arch_timing": {
@@ -68,7 +68,7 @@
6868
"generated_blif": "syn7_generated.blif",
6969
"exit": 134,
7070
"errors": [
71-
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_add~0 to a valid type."
71+
"[SIMULATION] Could not resolve memory hard block fpu_add~0 to a valid type."
7272
]
7373
},
7474
"DEFAULT": {

‎ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -36,42 +36,42 @@
3636
"generated_blif": "always_clk_generated.blif",
3737
"exit": 134,
3838
"errors": [
39-
"[OUTPUT_BLIF] Vector files differ."
39+
"[SIMULATION] Vector files differ."
4040
],
4141
"warnings": [
42-
"[OUTPUT_BLIF] Vector 2 mismatch:",
43-
"[OUTPUT_BLIF] Vector 3 mismatch:",
44-
"[OUTPUT_BLIF] Vector 6 mismatch:",
45-
"[OUTPUT_BLIF] Vector 7 mismatch:",
46-
"[OUTPUT_BLIF] Vector 26 mismatch:",
47-
"[OUTPUT_BLIF] Vector 27 mismatch:",
48-
"[OUTPUT_BLIF] Vector 30 mismatch:",
49-
"[OUTPUT_BLIF] Vector 31 mismatch:"
42+
"[SIMULATION] Vector 2 mismatch:",
43+
"[SIMULATION] Vector 3 mismatch:",
44+
"[SIMULATION] Vector 6 mismatch:",
45+
"[SIMULATION] Vector 7 mismatch:",
46+
"[SIMULATION] Vector 26 mismatch:",
47+
"[SIMULATION] Vector 27 mismatch:",
48+
"[SIMULATION] Vector 30 mismatch:",
49+
"[SIMULATION] Vector 31 mismatch:"
5050
]
5151
},
5252
"always/always_posedge_negedge/no_arch": {
5353
"test_name": "always/always_posedge_negedge/no_arch",
5454
"generated_blif": "always_posedge_negedge_generated.blif",
5555
"exit": 134,
5656
"errors": [
57-
"[OUTPUT_BLIF] Vector files differ."
57+
"[SIMULATION] Vector files differ."
5858
],
5959
"warnings": [
60-
"[OUTPUT_BLIF] Vector 2 mismatch:",
61-
"[OUTPUT_BLIF] Vector 3 mismatch:",
62-
"[OUTPUT_BLIF] Vector 6 mismatch:",
63-
"[OUTPUT_BLIF] Vector 7 mismatch:",
64-
"[OUTPUT_BLIF] Vector 26 mismatch:",
65-
"[OUTPUT_BLIF] Vector 27 mismatch:",
66-
"[OUTPUT_BLIF] Vector 30 mismatch:",
67-
"[OUTPUT_BLIF] Vector 31 mismatch:"
60+
"[SIMULATION] Vector 2 mismatch:",
61+
"[SIMULATION] Vector 3 mismatch:",
62+
"[SIMULATION] Vector 6 mismatch:",
63+
"[SIMULATION] Vector 7 mismatch:",
64+
"[SIMULATION] Vector 26 mismatch:",
65+
"[SIMULATION] Vector 27 mismatch:",
66+
"[SIMULATION] Vector 30 mismatch:",
67+
"[SIMULATION] Vector 31 mismatch:"
6868
]
6969
},
7070
"always/always_asterisk_event/no_arch": {
7171
"test_name": "always/always_asterisk_event/no_arch",
7272
"generated_blif": "always_asterisk_event_generated.blif",
7373
"warnings": [
74-
"[OUTPUT_BLIF] Vector 0 equivalent but output vector has bits set when expecting don't care :"
74+
"[SIMULATION] Vector 0 equivalent but output vector has bits set when expecting don't care :"
7575
],
7676
"max_rss(MiB)": 30,
7777
"exec_time(ms)": 3.4,
@@ -89,7 +89,7 @@
8989
"test_name": "always/always_lone_asterisk/no_arch",
9090
"generated_blif": "always_lone_asterisk_generated.blif",
9191
"warnings": [
92-
"[OUTPUT_BLIF] Vector 0 equivalent but output vector has bits set when expecting don't care :"
92+
"[SIMULATION] Vector 0 equivalent but output vector has bits set when expecting don't care :"
9393
],
9494
"max_rss(MiB)": 29.8,
9595
"exec_time(ms)": 3.5,
@@ -108,17 +108,17 @@
108108
"generated_blif": "always_or_event_generated.blif",
109109
"exit": 134,
110110
"errors": [
111-
"[OUTPUT_BLIF] Vector files differ."
111+
"[SIMULATION] Vector files differ."
112112
],
113113
"warnings": [
114-
"[OUTPUT_BLIF] Vector 0 equivalent but output vector has bits set when expecting don't care :",
115-
"[OUTPUT_BLIF] Vector 1 equivalent but output vector has bits set when expecting don't care :",
116-
"[OUTPUT_BLIF] Vector 2 equivalent but output vector has bits set when expecting don't care :",
117-
"[OUTPUT_BLIF] Vector 3 equivalent but output vector has bits set when expecting don't care :",
118-
"[OUTPUT_BLIF] Vector 34 mismatch:",
119-
"[OUTPUT_BLIF] Vector 35 mismatch:",
120-
"[OUTPUT_BLIF] Vector 38 mismatch:",
121-
"[OUTPUT_BLIF] Vector 39 mismatch:"
114+
"[SIMULATION] Vector 0 equivalent but output vector has bits set when expecting don't care :",
115+
"[SIMULATION] Vector 1 equivalent but output vector has bits set when expecting don't care :",
116+
"[SIMULATION] Vector 2 equivalent but output vector has bits set when expecting don't care :",
117+
"[SIMULATION] Vector 3 equivalent but output vector has bits set when expecting don't care :",
118+
"[SIMULATION] Vector 34 mismatch:",
119+
"[SIMULATION] Vector 35 mismatch:",
120+
"[SIMULATION] Vector 38 mismatch:",
121+
"[SIMULATION] Vector 39 mismatch:"
122122
]
123123
},
124124
"DEFAULT": {

‎ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -17,28 +17,28 @@
1717
"generated_blif": "defparam_generated.blif",
1818
"exit": 134,
1919
"errors": [
20-
"[OUTPUT_BLIF] Vector files differ."
20+
"[SIMULATION] Vector files differ."
2121
],
2222
"warnings": [
23-
"[OUTPUT_BLIF] Vector 1 mismatch:",
24-
"[OUTPUT_BLIF] Vector 2 mismatch:",
25-
"[OUTPUT_BLIF] Vector 3 mismatch:",
26-
"[OUTPUT_BLIF] Vector 4 mismatch:",
27-
"[OUTPUT_BLIF] Vector 5 mismatch:",
28-
"[OUTPUT_BLIF] Vector 6 mismatch:",
29-
"[OUTPUT_BLIF] Vector 7 mismatch:",
30-
"[OUTPUT_BLIF] Vector 9 mismatch:",
31-
"[OUTPUT_BLIF] Vector 14 mismatch:",
32-
"[OUTPUT_BLIF] Vector 17 mismatch:",
33-
"[OUTPUT_BLIF] Vector 18 mismatch:",
34-
"[OUTPUT_BLIF] Vector 21 mismatch:",
35-
"[OUTPUT_BLIF] Vector 22 mismatch:",
36-
"[OUTPUT_BLIF] Vector 24 mismatch:",
37-
"[OUTPUT_BLIF] Vector 25 mismatch:",
38-
"[OUTPUT_BLIF] Vector 28 mismatch:",
39-
"[OUTPUT_BLIF] Vector 31 mismatch:",
40-
"[OUTPUT_BLIF] Vector 32 mismatch:",
41-
"[OUTPUT_BLIF] Vector 35 mismatch:"
23+
"[SIMULATION] Vector 1 mismatch:",
24+
"[SIMULATION] Vector 2 mismatch:",
25+
"[SIMULATION] Vector 3 mismatch:",
26+
"[SIMULATION] Vector 4 mismatch:",
27+
"[SIMULATION] Vector 5 mismatch:",
28+
"[SIMULATION] Vector 6 mismatch:",
29+
"[SIMULATION] Vector 7 mismatch:",
30+
"[SIMULATION] Vector 9 mismatch:",
31+
"[SIMULATION] Vector 14 mismatch:",
32+
"[SIMULATION] Vector 17 mismatch:",
33+
"[SIMULATION] Vector 18 mismatch:",
34+
"[SIMULATION] Vector 21 mismatch:",
35+
"[SIMULATION] Vector 22 mismatch:",
36+
"[SIMULATION] Vector 24 mismatch:",
37+
"[SIMULATION] Vector 25 mismatch:",
38+
"[SIMULATION] Vector 28 mismatch:",
39+
"[SIMULATION] Vector 31 mismatch:",
40+
"[SIMULATION] Vector 32 mismatch:",
41+
"[SIMULATION] Vector 35 mismatch:"
4242
]
4343
},
4444
"defparam/defparam_string/no_arch": {
@@ -120,46 +120,46 @@
120120
"generated_blif": "defparam_depth_2_generated.blif",
121121
"exit": 134,
122122
"errors": [
123-
"[OUTPUT_BLIF] Vector files differ."
123+
"[SIMULATION] Vector files differ."
124124
],
125125
"warnings": [
126-
"[OUTPUT_BLIF] Vector 0 mismatch:",
127-
"[OUTPUT_BLIF] Vector 1 mismatch:",
128-
"[OUTPUT_BLIF] Vector 2 mismatch:",
129-
"[OUTPUT_BLIF] Vector 3 mismatch:",
130-
"[OUTPUT_BLIF] Vector 4 mismatch:",
131-
"[OUTPUT_BLIF] Vector 5 mismatch:",
132-
"[OUTPUT_BLIF] Vector 6 mismatch:",
133-
"[OUTPUT_BLIF] Vector 7 mismatch:",
134-
"[OUTPUT_BLIF] Vector 8 mismatch:",
135-
"[OUTPUT_BLIF] Vector 9 mismatch:",
136-
"[OUTPUT_BLIF] Vector 10 mismatch:",
137-
"[OUTPUT_BLIF] Vector 11 mismatch:",
138-
"[OUTPUT_BLIF] Vector 12 mismatch:",
139-
"[OUTPUT_BLIF] Vector 13 mismatch:",
140-
"[OUTPUT_BLIF] Vector 14 mismatch:",
141-
"[OUTPUT_BLIF] Vector 15 mismatch:",
142-
"[OUTPUT_BLIF] Vector 16 mismatch:",
143-
"[OUTPUT_BLIF] Vector 17 mismatch:",
144-
"[OUTPUT_BLIF] Vector 18 mismatch:",
145-
"[OUTPUT_BLIF] Vector 19 mismatch:",
146-
"[OUTPUT_BLIF] Vector 20 mismatch:",
147-
"[OUTPUT_BLIF] Vector 21 mismatch:",
148-
"[OUTPUT_BLIF] Vector 22 mismatch:",
149-
"[OUTPUT_BLIF] Vector 23 mismatch:",
150-
"[OUTPUT_BLIF] Vector 24 mismatch:",
151-
"[OUTPUT_BLIF] Vector 25 mismatch:",
152-
"[OUTPUT_BLIF] Vector 26 mismatch:",
153-
"[OUTPUT_BLIF] Vector 27 mismatch:",
154-
"[OUTPUT_BLIF] Vector 28 mismatch:",
155-
"[OUTPUT_BLIF] Vector 29 mismatch:",
156-
"[OUTPUT_BLIF] Vector 30 mismatch:",
157-
"[OUTPUT_BLIF] Vector 32 mismatch:",
158-
"[OUTPUT_BLIF] Vector 33 mismatch:",
159-
"[OUTPUT_BLIF] Vector 34 mismatch:",
160-
"[OUTPUT_BLIF] Vector 35 mismatch:",
161-
"[OUTPUT_BLIF] Vector 36 mismatch:",
162-
"[OUTPUT_BLIF] Vector 37 mismatch:"
126+
"[SIMULATION] Vector 0 mismatch:",
127+
"[SIMULATION] Vector 1 mismatch:",
128+
"[SIMULATION] Vector 2 mismatch:",
129+
"[SIMULATION] Vector 3 mismatch:",
130+
"[SIMULATION] Vector 4 mismatch:",
131+
"[SIMULATION] Vector 5 mismatch:",
132+
"[SIMULATION] Vector 6 mismatch:",
133+
"[SIMULATION] Vector 7 mismatch:",
134+
"[SIMULATION] Vector 8 mismatch:",
135+
"[SIMULATION] Vector 9 mismatch:",
136+
"[SIMULATION] Vector 10 mismatch:",
137+
"[SIMULATION] Vector 11 mismatch:",
138+
"[SIMULATION] Vector 12 mismatch:",
139+
"[SIMULATION] Vector 13 mismatch:",
140+
"[SIMULATION] Vector 14 mismatch:",
141+
"[SIMULATION] Vector 15 mismatch:",
142+
"[SIMULATION] Vector 16 mismatch:",
143+
"[SIMULATION] Vector 17 mismatch:",
144+
"[SIMULATION] Vector 18 mismatch:",
145+
"[SIMULATION] Vector 19 mismatch:",
146+
"[SIMULATION] Vector 20 mismatch:",
147+
"[SIMULATION] Vector 21 mismatch:",
148+
"[SIMULATION] Vector 22 mismatch:",
149+
"[SIMULATION] Vector 23 mismatch:",
150+
"[SIMULATION] Vector 24 mismatch:",
151+
"[SIMULATION] Vector 25 mismatch:",
152+
"[SIMULATION] Vector 26 mismatch:",
153+
"[SIMULATION] Vector 27 mismatch:",
154+
"[SIMULATION] Vector 28 mismatch:",
155+
"[SIMULATION] Vector 29 mismatch:",
156+
"[SIMULATION] Vector 30 mismatch:",
157+
"[SIMULATION] Vector 32 mismatch:",
158+
"[SIMULATION] Vector 33 mismatch:",
159+
"[SIMULATION] Vector 34 mismatch:",
160+
"[SIMULATION] Vector 35 mismatch:",
161+
"[SIMULATION] Vector 36 mismatch:",
162+
"[SIMULATION] Vector 37 mismatch:"
163163
]
164164
},
165165
"DEFAULT": {

‎ODIN_II/regression_test/benchmark/task/keywords/if/simulation_result.json

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -3,24 +3,24 @@
33
"test_name": "if/if_statement/no_arch",
44
"generated_blif": "if_statement_generated.blif",
55
"warnings": [
6-
"[OUTPUT_BLIF] Vector 5 equivalent but output vector has bits set when expecting don't care :",
7-
"[OUTPUT_BLIF] Vector 8 equivalent but output vector has bits set when expecting don't care :",
8-
"[OUTPUT_BLIF] Vector 10 equivalent but output vector has bits set when expecting don't care :",
9-
"[OUTPUT_BLIF] Vector 14 equivalent but output vector has bits set when expecting don't care :",
10-
"[OUTPUT_BLIF] Vector 15 equivalent but output vector has bits set when expecting don't care :",
11-
"[OUTPUT_BLIF] Vector 17 equivalent but output vector has bits set when expecting don't care :",
12-
"[OUTPUT_BLIF] Vector 18 equivalent but output vector has bits set when expecting don't care :",
13-
"[OUTPUT_BLIF] Vector 20 equivalent but output vector has bits set when expecting don't care :",
14-
"[OUTPUT_BLIF] Vector 24 equivalent but output vector has bits set when expecting don't care :",
15-
"[OUTPUT_BLIF] Vector 25 equivalent but output vector has bits set when expecting don't care :",
16-
"[OUTPUT_BLIF] Vector 27 equivalent but output vector has bits set when expecting don't care :",
17-
"[OUTPUT_BLIF] Vector 30 equivalent but output vector has bits set when expecting don't care :",
18-
"[OUTPUT_BLIF] Vector 31 equivalent but output vector has bits set when expecting don't care :",
19-
"[OUTPUT_BLIF] Vector 32 equivalent but output vector has bits set when expecting don't care :",
20-
"[OUTPUT_BLIF] Vector 33 equivalent but output vector has bits set when expecting don't care :",
21-
"[OUTPUT_BLIF] Vector 35 equivalent but output vector has bits set when expecting don't care :",
22-
"[OUTPUT_BLIF] Vector 36 equivalent but output vector has bits set when expecting don't care :",
23-
"[OUTPUT_BLIF] Vector 37 equivalent but output vector has bits set when expecting don't care :"
6+
"[SIMULATION] Vector 5 equivalent but output vector has bits set when expecting don't care :",
7+
"[SIMULATION] Vector 8 equivalent but output vector has bits set when expecting don't care :",
8+
"[SIMULATION] Vector 10 equivalent but output vector has bits set when expecting don't care :",
9+
"[SIMULATION] Vector 14 equivalent but output vector has bits set when expecting don't care :",
10+
"[SIMULATION] Vector 15 equivalent but output vector has bits set when expecting don't care :",
11+
"[SIMULATION] Vector 17 equivalent but output vector has bits set when expecting don't care :",
12+
"[SIMULATION] Vector 18 equivalent but output vector has bits set when expecting don't care :",
13+
"[SIMULATION] Vector 20 equivalent but output vector has bits set when expecting don't care :",
14+
"[SIMULATION] Vector 24 equivalent but output vector has bits set when expecting don't care :",
15+
"[SIMULATION] Vector 25 equivalent but output vector has bits set when expecting don't care :",
16+
"[SIMULATION] Vector 27 equivalent but output vector has bits set when expecting don't care :",
17+
"[SIMULATION] Vector 30 equivalent but output vector has bits set when expecting don't care :",
18+
"[SIMULATION] Vector 31 equivalent but output vector has bits set when expecting don't care :",
19+
"[SIMULATION] Vector 32 equivalent but output vector has bits set when expecting don't care :",
20+
"[SIMULATION] Vector 33 equivalent but output vector has bits set when expecting don't care :",
21+
"[SIMULATION] Vector 35 equivalent but output vector has bits set when expecting don't care :",
22+
"[SIMULATION] Vector 36 equivalent but output vector has bits set when expecting don't care :",
23+
"[SIMULATION] Vector 37 equivalent but output vector has bits set when expecting don't care :"
2424
],
2525
"max_rss(MiB)": 14.6,
2626
"exec_time(ms)": 5.6,

‎ODIN_II/regression_test/benchmark/task/keywords/initial/simulation_result.json

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,32 +4,32 @@
44
"generated_blif": "initial_delays_generated.blif",
55
"exit": 134,
66
"errors": [
7-
"[OUTPUT_BLIF] Vector files differ."
7+
"[SIMULATION] Vector files differ."
88
],
99
"warnings": [
10-
"[OUTPUT_BLIF] Simulation produced fewer than 6 vectors."
10+
"[SIMULATION] Simulation produced fewer than 6 vectors."
1111
]
1212
},
1313
"initial/initial_multiple_blocks/no_arch": {
1414
"test_name": "initial/initial_multiple_blocks/no_arch",
1515
"generated_blif": "initial_multiple_blocks_generated.blif",
1616
"exit": 134,
1717
"errors": [
18-
"[OUTPUT_BLIF] Vector files differ."
18+
"[SIMULATION] Vector files differ."
1919
],
2020
"warnings": [
21-
"[OUTPUT_BLIF] Simulation produced fewer than 8 vectors."
21+
"[SIMULATION] Simulation produced fewer than 8 vectors."
2222
]
2323
},
2424
"initial/initial_multiple_statements/no_arch": {
2525
"test_name": "initial/initial_multiple_statements/no_arch",
2626
"generated_blif": "initial_multiple_statements_generated.blif",
2727
"exit": 134,
2828
"errors": [
29-
"[OUTPUT_BLIF] Vector files differ."
29+
"[SIMULATION] Vector files differ."
3030
],
3131
"warnings": [
32-
"[OUTPUT_BLIF] Simulation produced fewer than 2 vectors."
32+
"[SIMULATION] Simulation produced fewer than 2 vectors."
3333
]
3434
},
3535
"DEFAULT": {

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