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flow: Update basic and strong reg test golden results
Tweaks to placer cost calculation have changed some optimiztaion results
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‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.56 0.02 8604 4 0.17 -1 -1 34060 -1 -1 72 99 1 0 aed1b2472 success 26076 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 604 0.20 30 1651 7 3.33e+06 2.28e+06 408126. 2414.95 0.58
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k4_N10_memSize16384_memData64.xml diffeq1.v common 2.30 0.02 7768 24 0.26 -1 -1 34324 -1 -1 70 162 0 5 aed1b2472 success 29720 162 96 1207 1144 1 690 333 13 13 169 clb auto 0.12 4460 0.32 50 10164 35 3.33e+06 2.55e+06 641417. 3795.37 0.83
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.15 0.03 8720 4 0.16 -1 -1 34028 -1 -1 72 99 1 0 v8.0.0-rc1-34-g650a1b901 success 20152 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 638 0.19 34 1649 14 3.33e+06 2.28e+06 450788. 2667.39 0.21
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k4_N10_memSize16384_memData64.xml diffeq1.v common 2.79 0.01 7836 24 0.22 -1 -1 34432 -1 -1 70 162 0 5 v8.0.0-rc1-34-g650a1b901 success 25244 162 96 1207 1144 1 690 333 13 13 169 clb auto 0.13 4486 0.32 52 9464 34 3.33e+06 2.55e+06 671819. 3975.26 1.29

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt

Lines changed: 3 additions & 3 deletions
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
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k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 0.05 8760 3 0.16 -1 -1 34312 -1 -1 71 99 1 0 aed1b2472 success 29256 99 130 363 493 1 256 301 13 13 169 clb auto 0.05 717 0.31 1.95494 -206.384 -1.95494 44 1275 18 6.63067e+06 4.37447e+06 414688. 2453.77 0.54 1135 13 797 1146 155766 55958 2.21795 -230.28 -2.21795 0 0 539786. 3194.00 0.03
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k6_N10_mem32K_40nm.xml diffeq1.v common 5.33 0.01 7844 15 0.26 -1 -1 34316 -1 -1 51 162 0 5 aed1b2472 success 44712 162 96 1001 938 1 705 314 16 16 256 mult_36 auto 0.14 5408 0.71 19.625 -1790.93 -19.625 52 9587 50 1.21132e+07 4.72859e+06 771607. 3014.09 3.12 8703 23 3355 6975 2825732 819848 21.4738 -1924.71 -21.4738 0 0 1.01513e+06 3965.34 0.30
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
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k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.37 0.04 8752 3 0.17 -1 -1 34360 -1 -1 71 99 1 0 v8.0.0-rc1-34-g650a1b901 success 21588 99 130 363 493 1 256 301 13 13 169 clb auto 0.05 694 0.29 2.04196 -209.545 -2.04196 42 1232 14 6.63067e+06 4.37447e+06 396943. 2348.77 0.22 1211 24 756 1060 202792 79081 2.32164 -230.648 -2.32164 0 0 498890. 2952.01 0.04
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k6_N10_mem32K_40nm.xml diffeq1.v common 5.11 0.01 7864 15 0.28 -1 -1 34396 -1 -1 51 162 0 5 v8.0.0-rc1-34-g650a1b901 success 31284 162 96 1001 938 1 705 314 16 16 256 mult_36 auto 0.15 5483 0.65 19.6677 -1759.31 -19.6677 46 10428 46 1.21132e+07 4.72859e+06 696785. 2721.82 2.99 9414 23 3561 7308 2552626 683332 21.4678 -1934.91 -21.4678 0 0 894618. 3494.60 0.27

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
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k6_N10_mem32K_40nm.xml mkPktMerge.v common 8.97 0.08 16644 2 0.08 -1 -1 34036 -1 -1 33 311 15 0 aed1b2472 success 57724 311 156 972 1128 1 954 515 28 28 784 memory auto 0.27 7729 1.27 3.68616 -4070.11 -3.68616 40 13458 30 4.25198e+07 9.9985e+06 2.03169e+06 2591.44 5.33 12621 24 2922 3354 4805862 1711800 3.984 -4708.19 -3.984 -9.97696 -0.29768 2.55406e+06 3257.73 0.57
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
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k6_N10_mem32K_40nm.xml mkPktMerge.v common 12.30 0.14 16704 2 0.09 -1 -1 34176 -1 -1 33 311 15 0 v8.0.0-rc1-34-g650a1b901 success 50756 311 156 972 1128 1 954 515 28 28 784 memory auto 0.28 7339 1.24 3.50082 -4199.76 -3.50082 36 13582 27 4.25198e+07 9.9985e+06 1.86960e+06 2384.70 8.46 12376 35 3518 3979 5974008 2193096 3.92354 -4832.49 -3.92354 -18.6448 -0.360359 2.30301e+06 2937.52 0.76

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