Skip to content

Commit b172d26

Browse files
tangxifantangxifan
committed
[vpr] now when cb on perimeter, I/O pins can access three sides
1 parent 97c106c commit b172d26

File tree

3 files changed

+64
-61
lines changed

3 files changed

+64
-61
lines changed

‎vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp

Lines changed: 42 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -43,26 +43,54 @@ int get_grid_pin_class_index(const DeviceGrid& grids,
4343
}
4444

4545
/* Deteremine the side of a io grid */
46-
e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
47-
const vtr::Point<size_t>& grid_coordinate) {
46+
std::vector<e_side> determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
47+
const vtr::Point<size_t>& grid_coordinate,
48+
const bool& perimeter_cb) {
49+
std::vector<e_side> pin_sides;
4850
/* TOP side IO of FPGA */
4951
if (device_size.y() == grid_coordinate.y()) {
50-
return BOTTOM; /* Such I/O has only Bottom side pins */
52+
/* Such I/O has only bottom side pins */
53+
pin_sides.push_back(BOTTOM);
54+
/* If cbs are allowed around boundary I/Os, add two more sides */
55+
if (perimeter_cb) {
56+
pin_sides.push_back(LEFT);
57+
pin_sides.push_back(RIGHT);
58+
}
5159
} else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */
52-
return LEFT; /* Such I/O has only Left side pins */
60+
/* Such I/O has only Left side pins */
61+
pin_sides.push_back(LEFT);
62+
/* If cbs are allowed around boundary I/Os, add two more sides */
63+
if (perimeter_cb) {
64+
pin_sides.push_back(TOP);
65+
pin_sides.push_back(BOTTOM);
66+
}
5367
} else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */
54-
return TOP; /* Such I/O has only Top side pins */
68+
/* Such I/O has only Top side pins */
69+
pin_sides.push_back(TOP);
70+
/* If cbs are allowed around boundary I/Os, add two more sides */
71+
if (perimeter_cb) {
72+
pin_sides.push_back(LEFT);
73+
pin_sides.push_back(RIGHT);
74+
}
5575
} else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */
56-
return RIGHT; /* Such I/O has only Right side pins */
76+
/* Such I/O has only Right side pins */
77+
pin_sides.push_back(RIGHT);
78+
/* If cbs are allowed around boundary I/Os, add two more sides */
79+
if (perimeter_cb) {
80+
pin_sides.push_back(TOP);
81+
pin_sides.push_back(BOTTOM);
82+
}
5783
} else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) {
5884
/* I/O grid in the center grid */
5985
return NUM_SIDES;
60-
}
61-
VTR_LOGF_ERROR(__FILE__, __LINE__,
62-
"Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n",
63-
grid_coordinate.x(), grid_coordinate.y(),
64-
device_size.x(), device_size.y());
65-
exit(1);
86+
} else {
87+
VTR_LOGF_ERROR(__FILE__, __LINE__,
88+
"Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n",
89+
grid_coordinate.x(), grid_coordinate.y(),
90+
device_size.x(), device_size.y());
91+
exit(1);
92+
}
93+
return pin_sides;
6694
}
6795

6896
/* Deteremine the side of a pin of a grid */
@@ -124,17 +152,12 @@ size_t get_grid_num_pins(const DeviceGrid& grids,
124152
const size_t& x,
125153
const size_t& y,
126154
const e_pin_type& pin_type,
127-
const e_side& io_side) {
155+
const std::vector<e_side>& io_side) {
128156
size_t num_pins = 0;
129157

130158
/* For IO_TYPE sides */
131159
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer));
132-
for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) {
133-
/* skip unwanted sides */
134-
if ((true == is_io_type(phy_tile_type))
135-
&& (side != io_side) && (NUM_SIDES != io_side)) {
136-
continue;
137-
}
160+
for (const e_side& side : io_side) {
138161
/* Get pin list */
139162
for (int width = 0; width < phy_tile_type->width; ++width) {
140163
for (int height = 0; height < phy_tile_type->height; ++height) {

‎vpr/src/tileable_rr_graph/rr_graph_builder_utils.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,9 @@ std::vector<e_side> find_grid_pin_sides(const DeviceGrid& grids,
2727
const size_t& y,
2828
const size_t& pin_id);
2929

30-
e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
31-
const vtr::Point<size_t>& grid_coordinate);
30+
std::vector<e_side> determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
31+
const vtr::Point<size_t>& grid_coordinate,
32+
const bool& perimeter_cb);
3233

3334
std::vector<int> get_grid_side_pins(const DeviceGrid& grids,
3435
const size_t& layer,
@@ -44,7 +45,7 @@ size_t get_grid_num_pins(const DeviceGrid& grids,
4445
const size_t& x,
4546
const size_t& y,
4647
const e_pin_type& pin_type,
47-
const e_side& io_side);
48+
const std::vector<e_side>& io_side);
4849

4950
size_t get_grid_num_classes(const DeviceGrid& grids,
5051
const size_t& layer,

‎vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

Lines changed: 18 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,8 @@
2626
***********************************************************************/
2727
static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids,
2828
const size_t& layer,
29-
const t_rr_type& node_type) {
29+
const t_rr_type& node_type,
30+
const bool& perimeter_cb) {
3031
size_t num_grid_rr_nodes = 0;
3132

3233
for (size_t ix = 0; ix < grids.width(); ++ix) {
@@ -43,13 +44,13 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids,
4344
continue;
4445
}
4546

46-
enum e_side io_side = NUM_SIDES;
47+
std::vector<e_side> io_side = {TOP, RIGHT, BOTTOM, LEFT};
4748

4849
/* If this is the block on borders, we consider IO side */
4950
if (true == is_io_type(grids.get_physical_type(tile_loc))) {
5051
vtr::Point<size_t> io_device_size(grids.width() - 1, grids.height() - 1);
5152
vtr::Point<size_t> grid_coordinate(ix, iy);
52-
io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate);
53+
io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb);
5354
}
5455

5556
switch (node_type) {
@@ -340,10 +341,10 @@ static std::vector<size_t> estimate_num_rr_nodes(const DeviceGrid& grids,
340341
/**
341342
* 1 Find number of rr nodes related to grids
342343
*/
343-
num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN);
344-
num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN);
345-
num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE);
346-
num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK);
344+
num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN, perimeter_cb);
345+
num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN, perimeter_cb);
346+
num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb);
347+
num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb);
347348

348349
/**
349350
* 2. Assign the segments for each routing channel,
@@ -432,24 +433,17 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder
432433
const size_t& layer,
433434
const vtr::Point<size_t>& grid_coordinate,
434435
const DeviceGrid& grids,
435-
const e_side& io_side,
436+
const std::vector<e_side>& wanted_sides,
436437
const RRSwitchId& delayless_switch) {
437-
SideManager io_side_manager(io_side);
438-
439438
/* Walk through the width height of each grid,
440439
* get pins and configure the rr_nodes
441440
*/
442441
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
443442
for (int width = 0; width < phy_tile_type->width; ++width) {
444443
for (int height = 0; height < phy_tile_type->height; ++height) {
445444
/* Walk through sides */
446-
for (e_side side : SIDES) {
445+
for (e_side side : wanted_sides) {
447446
SideManager side_manager(side);
448-
/* skip unwanted sides */
449-
if ((true == is_io_type(phy_tile_type))
450-
&& (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) {
451-
continue;
452-
}
453447
/* Find OPINs */
454448
/* Configure pins by pins */
455449
std::vector<int> opin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(),
@@ -497,7 +491,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder
497491
const size_t& layer,
498492
const vtr::Point<size_t>& grid_coordinate,
499493
const DeviceGrid& grids,
500-
const e_side& io_side,
494+
const std::vector<e_side>& wanted_sides,
501495
const RRSwitchId& wire_to_ipin_switch) {
502496
SideManager io_side_manager(io_side);
503497

@@ -508,14 +502,8 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder
508502
for (int width = 0; width < phy_tile_type->width; ++width) {
509503
for (int height = 0; height < phy_tile_type->height; ++height) {
510504
/* Walk through sides */
511-
for (e_side side : SIDES) {
505+
for (e_side side : wanted_sides) {
512506
SideManager side_manager(side);
513-
/* skip unwanted sides */
514-
if ((true == is_io_type(phy_tile_type))
515-
&& (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) {
516-
continue;
517-
}
518-
519507
/* Find IPINs */
520508
/* Configure pins by pins */
521509
std::vector<int> ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height);
@@ -562,10 +550,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build
562550
const size_t& layer,
563551
const vtr::Point<size_t>& grid_coordinate,
564552
const DeviceGrid& grids,
565-
const e_side& io_side,
566553
const RRSwitchId& delayless_switch) {
567-
SideManager io_side_manager(io_side);
568-
569554
/* Set a SOURCE rr_node for each DRIVER class */
570555
t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer);
571556
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc);
@@ -614,10 +599,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder
614599
const size_t& layer,
615600
const vtr::Point<size_t>& grid_coordinate,
616601
const DeviceGrid& grids,
617-
const e_side& io_side,
618602
const RRSwitchId& delayless_switch) {
619-
SideManager io_side_manager(io_side);
620-
621603
/* Set a SINK rr_node for each RECEIVER class */
622604
t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer);
623605
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc);
@@ -664,7 +646,8 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder,
664646
const DeviceGrid& grids,
665647
const size_t& layer,
666648
const RRSwitchId& wire_to_ipin_switch,
667-
const RRSwitchId& delayless_switch) {
649+
const RRSwitchId& delayless_switch,
650+
const bool& perimeter_cb) {
668651
for (size_t iy = 0; iy < grids.height(); ++iy) {
669652
for (size_t ix = 0; ix < grids.width(); ++ix) {
670653
t_physical_tile_loc tile_loc(ix, iy, layer);
@@ -687,9 +670,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder,
687670
/* If this is the block on borders, we consider IO side */
688671
if (true == is_io_type(grids.get_physical_type(tile_loc))) {
689672
vtr::Point<size_t> io_device_size(grids.width() - 1, grids.height() - 1);
690-
io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate);
691-
wanted_sides.clear();
692-
wanted_sides.push_back(io_side);
673+
wanted_sides = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb);
693674
}
694675

695676
for (e_side side : wanted_sides) {
@@ -709,7 +690,6 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder,
709690
rr_rc_data,
710691
layer, grid_coordinate,
711692
grids,
712-
io_side,
713693
delayless_switch);
714694

715695
/* Configure sink rr_nodes for this grid */
@@ -718,7 +698,6 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder,
718698
rr_rc_data,
719699
layer, grid_coordinate,
720700
grids,
721-
io_side,
722701
delayless_switch);
723702

724703
/* Configure opin rr_nodes for this grid */
@@ -727,7 +706,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder,
727706
rr_rc_data,
728707
layer, grid_coordinate,
729708
grids,
730-
io_side,
709+
wanted_sides,
731710
delayless_switch);
732711

733712
/* Configure ipin rr_nodes for this grid */
@@ -736,7 +715,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder,
736715
rr_rc_data,
737716
layer, grid_coordinate,
738717
grids,
739-
io_side,
718+
wanted_sides,
740719
wire_to_ipin_switch);
741720
}
742721
}
@@ -1231,7 +1210,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph,
12311210
rr_rc_data,
12321211
grids, layer,
12331212
wire_to_ipin_switch,
1234-
delayless_switch);
1213+
delayless_switch, perimeter_cb);
12351214

12361215
load_chanx_rr_nodes_basic_info(rr_graph,
12371216
rr_graph_builder,

0 commit comments

Comments
 (0)