equivalent tiles: added equivalent tile placement capability

This commit introduces two major features:
- introduce the tile concept in the architecture XML. Top level pb_type
is discarded and all the top level pb_type information are moved into
the tile tags. This will cause CI build to fail as all the architectures
do not include the tiles tag right now.

- introduce the possibility to place blocks in equivalent tiles (SLICEL
blocks into SLICEM ones). According to the XML architecture description
there could be tiles equivalent to others that can be used during the
placement step (this can bring to better placement solutions)

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/physical_types.cpp

@@ -142,6 +142,15 @@ std::vector<int> t_type_descriptor::get_clock_pins_indices () const {
     return indices;
 }
 
+bool t_type_descriptor::is_available_tile_index(int index_to_check) const {
+    auto search = this->available_tiles_indices.find(index_to_check);
+    if (search != available_tiles_indices.end()) {
+        return true;
+    }
+
+    return false;
+}
+
 /**
  * t_pb_graph_node
  */

libs/libarchfpga/src/physical_types.h

@@ -31,9 +31,9 @@
 #include <unordered_map>
 #include <string>
 #include <map>
-#include <unordered_map>
 #include <limits>
 #include <numeric>
+#include <unordered_set>
 
 #include "vtr_ndmatrix.h"
 #include "vtr_hash.h"
@@ -170,9 +170,22 @@ enum e_pin_location_distr {
 
 /* pb_type class */
 enum e_pb_type_class {
-	UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3
+    UNKNOWN_CLASS = 0,
+    LUT_CLASS = 1,
+    LATCH_CLASS = 2,
+    MEMORY_CLASS = 3,
+    NUM_CLASSES
 };
 
+// Set of all pb_type classes
+constexpr std::array<e_pb_type_class, NUM_CLASSES> TYPE_CLASSES = {
+    {UNKNOWN_CLASS, LUT_CLASS, LATCH_CLASS, MEMORY_CLASS} };
+
+// String versions of pb_type class values
+constexpr std::array<const char*, NUM_CLASSES> TYPE_CLASS_STRING = {
+    {"unknown", "lut", "flipflop", "memory"} };
+
+
 /* Annotations for pin-to-pin connections */
 enum e_pin_to_pin_annotation_type {
 	E_ANNOT_PIN_TO_PIN_DELAY = 0,
@@ -535,6 +548,20 @@ constexpr int DEFAULT_SWITCH = -2;
  * pb_type: Internal subblocks and routing information for this physical block
  * pb_graph_head: Head of DAG of pb_types_nodes and their edges
  *
+ *
+ * num_equivalent_tiles: Specifies the number of equivalent physical types that can be used during placement.
+ *                       If the value is `0` all the data structures relative to the equivalent tiles will be empty.
+ * equivalent_tiles: Array containing pointers to the equivalent tiles. The number of elements contained is specified
+ *                   by num_equivalent_tiles.
+ * equivalent_tile_pin_mapping: Multi-dimensional array that, for each different equivalent tile contains a mapping between
+ *                              the pins of the two tiles.
+ *                              Example: equivalent_tile_pin_mapping[eq_tile_index][pin_index] = equivalent_pin_index
+ *                              This is necessary to maintain consistency between two equivalent tiles that have the same pins
+ *                              defined with different indeces.
+ * equivalent_tile_inverse_pin_mapping: Multi-dimensional array that works as the previous one, but the mapping is inverse in this case.
+ *                                      Example: equivalent_tile_pin_mapping[eq_tile_index][equivalent_pin_index] = pin_index
+ * available_tiles_indices: unordered map used to have a fast lookup on the available tiles.
+ *
  * area: Describes how much area this logic block takes, if undefined, use default
  * type_timing_inf: timing information unique to this type
  * num_drivers: Total number of output drivers supplied
@@ -574,6 +601,13 @@ struct t_type_descriptor /* TODO rename this.  maybe physical type descriptor or
 	t_pb_type *pb_type = nullptr;
 	t_pb_graph_node *pb_graph_head = nullptr;
 
+	/* Equivalent tiles information */
+	int num_equivalent_tiles = 0;
+	std::unordered_map<int, t_type_descriptor *> equivalent_tiles; /* [0..num_equivalent_tiles-1] */
+	std::unordered_map<int, std::unordered_map<int, int>> equivalent_tile_pin_mapping; /* [0..num_equivalent_tiles-1][0..num_pins-1] */
+	std::unordered_map<int, std::unordered_map<int, int>> equivalent_tile_inverse_pin_mapping; /* [0..num_equivalent_tiles-1][0..num_pins-1] */
+	std::unordered_set<int> available_tiles_indices;
+
 	float area = 0;
 
 	/* This info can be determined from class_inf and pin_class but stored for faster access */
@@ -582,9 +616,16 @@ struct t_type_descriptor /* TODO rename this.  maybe physical type descriptor or
 
 	int index = -1; /* index of type descriptor in array (allows for index referencing) */
 
+	/***********
+	 * Methods *
+	 ***********/
+
     /* Returns the indices of pins that contain a clock for this physical logic block */
     std::vector<int> get_clock_pins_indices() const;
 
+	/* Returns a boolean set to True if the input index belongs to an available tile, False otherwise */
+	bool is_available_tile_index(int index_to_check) const;
+
 };
 typedef const t_type_descriptor* t_type_ptr;
 
@@ -864,6 +905,7 @@ struct t_pin_to_pin_annotation {
  *      pb_type: Pointer to the type of pb graph node this belongs to
  *      mode: parent mode of operation
  *      placement_index: there are a certain number of pbs available, this gives the index of the node
+ *      illegal_modes: vector containing illigal modes that result in conflicts during routing
  *      child_pb_graph_nodes: array of children pb graph nodes organized into modes
  *      parent_pb_graph_node: parent pb graph node
  */
@@ -873,6 +915,8 @@ class t_pb_graph_node {
 
 	int placement_index;
 
+	std::vector<int> illegal_modes;
+
 	t_pb_graph_pin **input_pins; /* [0..num_input_ports-1] [0..num_port_pins-1]*/
 	t_pb_graph_pin **output_pins; /* [0..num_output_ports-1] [0..num_port_pins-1]*/
 	t_pb_graph_pin **clock_pins; /* [0..num_clock_ports-1] [0..num_port_pins-1]*/
@@ -1153,6 +1197,7 @@ struct t_segment_inf {
 	std::vector<bool> cb;
 	std::vector<bool> sb;
 	//float Cmetal_per_m; /* Wire capacitance (per meter) */
+	t_metadata_dict *meta = nullptr;
 };
 
 enum class SwitchType {