File tree 15 files changed +88
-88
lines changed
vtr_flow/tasks/regression_tests
strong_cin_tie_off/config
strong_global_nonuniform/config
strong_post_routing_sync/config
strong_cin_tie_off/config
strong_fix_pins_random/config
strong_post_routing_sync/config
15 files changed +88
-88
lines changed Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- k4_n4_v7_bidir.xml styr.blif common 1.48 vpr 57.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3 .0 on Linux-5.15 .0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic /vtr-verilog-to-routing 58568 10 10 253 263 1 169 87 11 11 121 clb auto 19.0 MiB 0.04 1270 57.2 MiB 0.04 0.00 5.46016 -69.6089 -5.46016 5.46016 0.13 0.000215331 0.000171987 0.00792391 0.00665338 13 1998 44 2.43e+06 2.01e +06 -1 -1 0.67 0.0832184 0.0722661 2006 27 1483 4679 322103 41342 9.23088 9.23088 -107.619 -9.23088 0 0 -1 -1 0.03 0.08 0.0198743 0.0176388
3- k4_n4_v7_longline_bidir.xml styr.blif common 2.03 vpr 57.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3 .0 on Linux-5.15 .0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic /vtr-verilog-to-routing 58680 10 10 253 263 1 169 87 11 11 121 clb auto 19.1 MiB 0.04 1274 57.3 MiB 0.04 0.00 5.85046 -74.2233 -5.85046 5.85046 0.19 0.000232214 0.000188182 0.00878653 0.00745938 18 2532 43 2.43e+06 2.01e +06 -1 -1 0.88 0.0924504 0.0755557 2435 38 2098 6378 540887 56511 9.2499 9.2499 -108.539 -9.2499 0 0 -1 -1 0.07 0.11 0.0228221 0.0199636
4- k4_n4_v7_l1_bidir.xml styr.blif common 2.31 vpr 57.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3 .0 on Linux-5.15 .0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic /vtr-verilog-to-routing 58420 10 10 253 263 1 169 87 11 11 121 clb auto 18.8 MiB 0.04 1314 57.1 MiB 0.05 0.00 7.03989 -83.5605 -7.03989 7.03989 0.17 0.000198421 0.000157186 0.0109691 0.00909187 11 1696 38 2.43e+06 2.01e +06 -1 -1 1.33 0.0788319 0.0684137 1347 23 1338 4185 371579 77951 8.29094 8.29094 -101.157 -8.29094 0 0 -1 -1 0.04 0.10 0.0180735 0.0162332
5- k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.59 vpr 57.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3 .0 on Linux-5.15 .0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic /vtr-verilog-to-routing 58404 10 10 253 263 1 169 87 11 11 121 clb auto 18.8 MiB 0.04 1338 57.0 MiB 0.06 0.00 6.19376 -68.5604 -6.19376 6.19376 0.46 0.000203538 0.000160851 0.0127857 0.0106469 16 2173 41 2.43e+06 2.01e +06 -1 -1 1.21 0.0981799 0.0859522 2120 27 1736 5578 1452395 185427 17.5032 17.5032 -249.6 -17.5032 0 0 -1 -1 0.04 0.26 0.0209466 0.0188615
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ k4_n4_v7_bidir.xml styr.blif common 1.48 vpr 60.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.8 .0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing /vtr-verilog-to-routing 61704 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1321 5000 862 3861 277 60.3 MiB 0.03 0.00 5.9335 -73.3937 -5.9335 5.9335 0.11 0.000261327 0.000224398 0.00853268 0.00751629 16 2231 44 2.43e+06 1.98e +06 -1 -1 0.82 0.103535 0.088869 3522 30407 -1 1953 31 1359 4378 262510 29492 8.05167 8.05167 -93.2354 -8.05167 0 0 -1 -1 0.04 0.05 0.01 -1 -1 0.04 0.0186186 0.0166315
3+ k4_n4_v7_longline_bidir.xml styr.blif common 1.35 vpr 60.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.8 .0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing /vtr-verilog-to-routing 61660 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1283 3299 376 2835 88 60.2 MiB 0.02 0.00 4.65232 -54.7485 -4.65232 4.65232 0.17 0.000261335 0.000226611 0.00623888 0.00553939 18 2324 34 2.43e+06 1.98e +06 -1 -1 0.50 0.0674339 0.0582272 3282 34431 -1 2358 20 1330 4111 330217 37900 9.15177 9.15177 -106.099 -9.15177 0 0 -1 -1 0.08 0.05 0.01 -1 -1 0.08 0.0141075 0.0127004
4+ k4_n4_v7_l1_bidir.xml styr.blif common 1.68 vpr 60.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.8 .0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing /vtr-verilog-to-routing 61736 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1308 8591 1804 6310 477 60.3 MiB 0.05 0.00 7.13454 -91.9395 -7.13454 7.13454 0.16 0.00024201 0.00020955 0.0132111 0.0116469 11 1687 50 2.43e+06 1.98e +06 -1 -1 0.85 0.0715403 0.0620252 4842 26197 -1 1434 21 1413 4826 393565 72389 8.93712 8.93712 -111.541 -8.93712 0 0 -1 -1 0.04 0.07 0.01 -1 -1 0.04 0.0141585 0.0126514
5+ k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.75 vpr 60.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 10 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.8 .0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing /vtr-verilog-to-routing 61708 10 10 253 263 1 168 86 11 11 121 clb auto 21.9 MiB 0.03 1271 3677 486 3031 160 60.3 MiB 0.03 0.00 3.40634 -44.4904 -3.40634 3.40634 0.12 0.000249094 0.000211604 0.00674832 0.00592154 16 2163 32 2.43e+06 1.98e +06 -1 -1 0.92 0.0676003 0.058382 3522 30407 -1 2237 32 1642 5759 1828879 289403 29.985 29.985 -297.537 -29.985 0 0 -1 -1 0.04 0.21 0.01 -1 -1 0.04 0.0186587 0.0165112
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
2- k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.47 vpr 61.68 MiB -1 -1 0.14 17412 1 0.02 -1 -1 30092 -1 -1 3 9 0 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/ vtr-verilog-to-routing/vtr_flow/tasks 63160 9 8 75 70 1 34 20 5 5 25 clb auto 23.0 MiB 0.48 71 587 167 407 13 61 .7 MiB 0.01 0.00 2.64007 -28.8002 -2.64007 2.64007 0.02 0.00018874 0.0001749 0.00515172 0.00481814 26 158 12 151211 75605.7 37105.9 1484.24 0.07 0.0263968 0.0224852 1908 5841 -1 154 11 104 116 4129 2171 2.87707 2.87707 -34.6861 -2.87707 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00661492 0.00590698 13 18 -1 -1 -1 -1
3- k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 5.70 vpr 62.75 MiB -1 -1 0.19 17840 1 0.03 -1 -1 30428 -1 -1 7 19 0 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9 .4.0 on Linux-4.15 .0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/ vtr-verilog-to-routing/vtr_flow/tasks 64260 19 18 308 249 1 142 44 6 6 36 clb auto 24.5 MiB 3.72 448 3740 1050 2663 27 62 .8 MiB 0.06 0.00 4.88121 -99.2245 -4.88121 4.88121 0.05 0.00062533 0.000580812 0.0338073 0.0315436 52 1067 23 403230 176413 110337. 3064.92 0.72 0.238972 0.204378 4014 20275 -1 806 25 799 1471 58539 21843 5.26432 5.26432 -115.767 -5.26432 0 0 143382. 3982.83 0.01 0.06 0.02 -1 -1 0.01 0.0338988 0.0298411 55 83 -1 -1 -1 -1
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
2+ k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.93 vpr 65.66 MiB -1 -1 0.06 20352 1 0.01 -1 -1 35860 -1 -1 3 9 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.8 .0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 67236 9 8 75 70 1 34 20 5 5 25 clb auto 27.3 MiB 0.38 91 452 103 339 10 65 .7 MiB 0.00 0.00 2.64007 -28.7664 -2.64007 2.64007 0.02 7.4568e-05 6.6193e-05 0.00195079 0.00178739 38 154 16 151211 75605.7 48493.3 1939.73 0.11 0.0243483 0.0205304 2100 8065 -1 119 18 114 142 4814 2350 2.64007 2.64007 -31.8474 -2.64007 0 0 61632.8 2465.31 0.01 0.01 0.01 -1 -1 0.01 0.00485388 0.00446806 13 18 -1 -1 -1 -1
3+ k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.87 vpr 66.77 MiB -1 -1 0.08 20736 1 0.01 -1 -1 35944 -1 -1 7 19 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11 .4.0 on Linux-6.8 .0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/ vtr-verilog-to-routing/vtr-verilog-to-routing 68372 19 18 308 249 1 142 44 6 6 36 clb auto 28.4 MiB 2.88 521 2662 840 1802 20 66 .8 MiB 0.02 0.00 4.88121 -98.944 -4.88121 4.88121 0.04 0.000207626 0.000184303 0.0103914 0.00951356 54 1083 35 403230 176413 113905. 3164.04 0.39 0.0844877 0.0734258 4050 20995 -1 745 17 630 985 35752 13957 5.5504 5.5504 -118.789 -5.5504 0 0 146644. 4073.44 0.01 0.02 0.01 -1 -1 0.01 0.014306 0.0132257 55 83 -1 -1 -1 -1
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