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mtdudekacomodi
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Misc fixes and comments
Signed-off-by: Maciej Dudek <[email protected]>
1 parent 5885628 commit ad2bdf4

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6 files changed

+139
-88
lines changed

6 files changed

+139
-88
lines changed

libs/libarchfpga/src/fpga_interchange_arch_utils.cpp

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,3 +76,24 @@ float get_corner_value(DeviceResources::Device::CornerModel::Reader model, const
7676
}
7777
return 0.;
7878
}
79+
80+
void fill_switch(t_rr_switch_inf& switch_,
81+
float R,
82+
float Cin,
83+
float Cout,
84+
float Cinternal,
85+
float Tdel,
86+
float mux_trans_size,
87+
float buf_size,
88+
char* name,
89+
SwitchType type) {
90+
switch_.R = R;
91+
switch_.Cin = Cin;
92+
switch_.Cout = Cout;
93+
switch_.Cinternal = Cinternal;
94+
switch_.Tdel = Tdel;
95+
switch_.mux_trans_size = mux_trans_size;
96+
switch_.buf_size = buf_size;
97+
switch_.name = name;
98+
switch_.set_type(type);
99+
}

libs/libarchfpga/src/fpga_interchange_arch_utils.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,17 @@ extern "C" {
3434

3535
float get_corner_value(DeviceResources::Device::CornerModel::Reader model, const char* speed_model, const char* value);
3636

37+
void fill_switch(t_rr_switch_inf& switch_,
38+
float R,
39+
float Cin,
40+
float Cout,
41+
float Cinternal,
42+
float Tdel,
43+
float mux_trans_size,
44+
float buf_size,
45+
char* name,
46+
SwitchType type);
47+
3748
#ifdef __cplusplus
3849
}
3950
#endif

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,29 @@ static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string
183183
return pp;
184184
}
185185

186+
void add_segment_with_default_values(t_segment_inf& seg, std::string name) {
187+
// Use default values as we will populate rr_graph with correct values
188+
// This segments are just declaration of future use
189+
seg.name = name;
190+
seg.length = 1;
191+
seg.frequency = 1;
192+
seg.Rmetal = 1e-12;
193+
seg.Cmetal = 1e-12;
194+
seg.parallel_axis = BOTH_AXIS;
195+
196+
// TODO: Only bi-directional segments are created, but it the interchange format
197+
// has directionality information on PIPs, which may be used to infer the
198+
// segments' directonality.
199+
seg.directionality = BI_DIRECTIONAL;
200+
seg.arch_wire_switch = 1;
201+
seg.arch_opin_switch = 1;
202+
seg.cb.resize(1);
203+
seg.cb[0] = true;
204+
seg.sb.resize(2);
205+
seg.sb[0] = true;
206+
seg.sb[1] = true;
207+
}
208+
186209
/****************** End Utility functions ******************/
187210

188211
struct ArchReader {
@@ -2370,29 +2393,6 @@ struct ArchReader {
23702393
}
23712394
}
23722395

2373-
void add_segment_with_default_values(t_segment_inf& seg, std::string name) {
2374-
// Use default values as we will populate rr_graph with correct values
2375-
// This segments are just declaration of future use
2376-
seg.name = name;
2377-
seg.length = 1;
2378-
seg.frequency = 1;
2379-
seg.Rmetal = 1e-12;
2380-
seg.Cmetal = 1e-12;
2381-
seg.parallel_axis = BOTH_AXIS;
2382-
2383-
// TODO: Only bi-directional segments are created, but it the interchange format
2384-
// has directionality information on PIPs, which may be used to infer the
2385-
// segments' directonality.
2386-
seg.directionality = BI_DIRECTIONAL;
2387-
seg.arch_wire_switch = 1;
2388-
seg.arch_opin_switch = 1;
2389-
seg.cb.resize(1);
2390-
seg.cb[0] = true;
2391-
seg.sb.resize(2);
2392-
seg.sb[0] = true;
2393-
seg.sb[1] = true;
2394-
}
2395-
23962396
void process_segments() {
23972397
// Segment names will be taken from wires connected to pips
23982398
// They are good representation for nodes

vpr/src/route/rr_graph.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -318,7 +318,7 @@ void create_rr_graph(const t_graph_type graph_type,
318318
auto& mutable_device_ctx = g_vpr_ctx.mutable_device();
319319

320320
if (!det_routing_arch->read_rr_graph_filename.empty() || router_opts.FPGAInterchange) {
321-
if (device_ctx.read_rr_graph_filename != det_routing_arch->read_rr_graph_filename && !router_opts.FPGAInterchange) {
321+
if (device_ctx.read_rr_graph_filename != det_routing_arch->read_rr_graph_filename) {
322322
free_rr_graph();
323323

324324
load_rr_file(graph_type,
@@ -343,6 +343,7 @@ void create_rr_graph(const t_graph_type graph_type,
343343
segment_inf,
344344
router_opts.base_cost_type,
345345
&det_routing_arch->wire_to_rr_ipin_switch,
346+
det_routing_arch->read_rr_graph_filename,
346347
router_opts.do_check_rr_graph);
347348
if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) {
348349
mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm,

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