doc: vpr: cmd: document --gen_post_synthesis_merged_netlist

Signed-off-by: Pawel Czarnecki <[email protected]>

Author: lpawelcz

doc/src/vpr/command_line_usage.rst

@@ -1254,6 +1254,14 @@ Analysis Options
 
     **Default:** ``off``
 
+.. option:: --gen_post_synthesis_merged_netlist { on | off }
+
+    This option is based on ``--gen_post_synthesis_netlist``.
+    The difference is that ``--gen_post_synthesis_merged_netlist`` generates only single verilog file with merged top module multi-bit ports of the implemented circuit.
+    The name of the file is ``<basename>_merged_post_synthesis.v``
+
+    **Default:** ``off``
+
 .. option:: --post_synth_netlist_unconn_inputs { unconnected | nets | gnd | vcc }
 
     Controls how unconnected input cell ports are handled in the post-synthesis netlist