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- #include < cstdio>
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- #include < cstring>
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#include < cmath>
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#include < set>
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#include " route_tree.h"
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#include " vtr_assert.h"
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#include " vtr_log.h"
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- #include " vtr_math.h"
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#include " vtr_ndmatrix.h"
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#include " vpr_types.h"
@@ -55,12 +52,10 @@ void routing_stats(const Netlist<>& net_list,
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enum e_directionality directionality,
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int wire_to_ipin_switch,
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bool is_flat) {
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- float area, used_area;
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-
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auto & device_ctx = g_vpr_ctx.device ();
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auto & rr_graph = device_ctx.rr_graph ;
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auto & cluster_ctx = g_vpr_ctx.clustering ();
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- auto & block_locs = g_vpr_ctx.placement ().block_locs ();
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+ const auto & block_locs = g_vpr_ctx.placement ().block_locs ();
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int num_rr_switch = rr_graph.num_rr_switches ();
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@@ -70,7 +65,7 @@ void routing_stats(const Netlist<>& net_list,
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VTR_LOG (" Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...\n " );
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- area = 0 ;
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+ float area = 0 ;
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for (int layer_num = 0 ; layer_num < device_ctx.grid .get_num_layers (); layer_num++) {
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for (int i = 0 ; i < (int )device_ctx.grid .width (); i++) {
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for (int j = 0 ; j < (int )device_ctx.grid .height (); j++) {
@@ -93,7 +88,7 @@ void routing_stats(const Netlist<>& net_list,
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/* Todo: need to add pitch of routing to blocks with height > 3 */
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VTR_LOG (" \t Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): %g\n " , area);
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- used_area = 0 ;
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+ float used_area = 0 ;
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for (ClusterBlockId blk_id : cluster_ctx.clb_nlist .blocks ()) {
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t_pl_loc block_loc = block_locs[blk_id].loc ;
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auto type = physical_tile_type (block_loc);
@@ -123,26 +118,20 @@ void routing_stats(const Netlist<>& net_list,
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* and net length in the routing.
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*/
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void length_and_bends_stats (const Netlist<>& net_list, bool is_flat) {
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- int bends, total_bends, max_bends;
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- int length, total_length, max_length;
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- int segments, total_segments, max_segments;
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- float av_bends, av_length, av_segments;
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- int num_global_nets, num_clb_opins_reserved, num_absorbed_nets;
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-
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- bool is_absorbed;
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-
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- max_bends = 0 ;
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- total_bends = 0 ;
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- max_length = 0 ;
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- total_length = 0 ;
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- max_segments = 0 ;
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- total_segments = 0 ;
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- num_global_nets = 0 ;
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- num_clb_opins_reserved = 0 ;
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- num_absorbed_nets = 0 ;
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+ int max_bends = 0 ;
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+ int total_bends = 0 ;
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+ int max_length = 0 ;
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+ int total_length = 0 ;
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+ int max_segments = 0 ;
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+ int total_segments = 0 ;
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+ int num_global_nets = 0 ;
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+ int num_clb_opins_reserved = 0 ;
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+ int num_absorbed_nets = 0 ;
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for (auto net_id : net_list.nets ()) {
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if (!net_list.net_is_ignored (net_id) && net_list.net_sinks (net_id).size () != 0 ) { /* Globals don't count. */
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+ int bends, length, segments;
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+ bool is_absorbed;
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get_num_bends_and_length (net_id, &bends, &length, &segments, &is_absorbed);
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total_bends += bends;
@@ -165,20 +154,20 @@ void length_and_bends_stats(const Netlist<>& net_list, bool is_flat) {
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}
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}
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- av_bends = (float )total_bends / (float )((int )net_list.nets ().size () - num_global_nets);
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+ float av_bends = (float )total_bends / (float )((int )net_list.nets ().size () - num_global_nets);
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VTR_LOG (" \n " );
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VTR_LOG (" Average number of bends per net: %#g Maximum # of bends: %d\n " , av_bends, max_bends);
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VTR_LOG (" \n " );
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- av_length = (float )total_length / (float )((int )net_list.nets ().size () - num_global_nets);
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+ float av_length = (float )total_length / (float )((int )net_list.nets ().size () - num_global_nets);
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VTR_LOG (" Number of global nets: %d\n " , num_global_nets);
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VTR_LOG (" Number of routed nets (nonglobal): %d\n " , (int )net_list.nets ().size () - num_global_nets);
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VTR_LOG (" Wire length results (in units of 1 clb segments)...\n " );
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VTR_LOG (" \t Total wirelength: %d, average net length: %#g\n " , total_length, av_length);
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VTR_LOG (" \t Maximum net length: %d\n " , max_length);
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VTR_LOG (" \n " );
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- av_segments = (float )total_segments / (float )((int )net_list.nets ().size () - num_global_nets);
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+ float av_segments = (float )total_segments / (float )((int )net_list.nets ().size () - num_global_nets);
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VTR_LOG (" Wire length results in terms of physical segments...\n " );
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VTR_LOG (" \t Total wiring segments used: %d, average wire segments per net: %#g\n " , total_segments, av_segments);
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VTR_LOG (" \t Maximum segments used by a net: %d\n " , max_segments);
@@ -425,9 +414,7 @@ void print_wirelen_prob_dist(bool is_flat) {
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* (i.e. the clock when it is marked global).
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*/
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void print_lambda () {
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- int ipin;
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int num_inputs_used = 0 ;
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- float lambda;
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auto & cluster_ctx = g_vpr_ctx.clustering ();
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auto & block_locs = g_vpr_ctx.placement ().block_locs ();
@@ -437,7 +424,7 @@ void print_lambda() {
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auto type = physical_tile_type (block_loc);
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VTR_ASSERT (type != nullptr );
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if (!is_io_type (type)) {
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- for (ipin = 0 ; ipin < type->num_pins ; ipin++) {
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+ for (int ipin = 0 ; ipin < type->num_pins ; ipin++) {
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if (get_pin_type_from_pin_physical_num (type, ipin) == RECEIVER) {
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ClusterNetId net_id = cluster_ctx.clb_nlist .block_net (blk_id, ipin);
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if (net_id != ClusterNetId::INVALID ()) /* Pin is connected? */
@@ -448,7 +435,7 @@ void print_lambda() {
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}
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}
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- lambda = (float )num_inputs_used / (float )cluster_ctx.clb_nlist .blocks ().size ();
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+ float lambda = (float )num_inputs_used / (float )cluster_ctx.clb_nlist .blocks ().size ();
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VTR_LOG (" Average lambda (input pins used per clb) is: %g\n " , lambda);
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}
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