Merge remote-tracking branch 'upstream/master' into fix_parse_runtime

Author: jgoeders

.github/kokoro/steps/vtr-test.sh

@@ -45,7 +45,11 @@ echo "========================================"
 echo "Running Tests"
 echo "========================================"
 export VPR_NUM_WORKERS=1
+
+set +e
 ./run_reg_test.py $VTR_TEST $VTR_TEST_OPTIONS -j$NUM_CORES
+TEST_RESULT=$?
+set -e
 kill $MONITOR
 
 echo "========================================"
@@ -70,3 +74,5 @@ if [[ $(du -s | cut -d $'\t' -f 1) -gt $(expr 1024 \* 1024 \* 90) ]]; then
     echo "Working directory too large!"
     exit 1
 fi
+
+exit $TEST_RESULT

ODIN_II/SRC/implicit_memory.cpp

@@ -97,6 +97,39 @@ char is_valid_implicit_memory_reference_ast(char* instance_name_prefix, ast_node
         return false;
 }
 
+bool is_signal_list_connected_to_memory(implicit_memory* memory, signal_list_t* signals, const char* port_name) {
+    oassert(port_name);
+
+    bool signals_are_connected = true;
+    // is any port of the memory connected
+    if (memory->node->input_port_sizes) {
+        int i, j;
+        long pin_index = 0;
+        for (i = 0; i < memory->node->num_input_port_sizes; i++) {
+            int input_port_size = memory->node->input_port_sizes[i];
+
+            for (j = 0; signals_are_connected && (input_port_size == signals->count) && j < signals->count; j++) {
+                npin_t* memory_input_pin = memory->node->input_pins[pin_index + j];
+
+                if (!strcmp(memory_input_pin->mapping, port_name)) {
+                    if (memory_input_pin->net->name && signals->pins[j]->net->name) {
+                        if (strcmp(memory_input_pin->net->name, signals->pins[j]->net->name)) {
+                            signals_are_connected = false;
+                        }
+                    } else {
+                        signals_are_connected = false;
+                    }
+                }
+            }
+            pin_index += input_port_size;
+        }
+    } else {
+        signals_are_connected = false;
+    }
+
+    return signals_are_connected;
+}
+
 /*
  * Creates an implicit memory block with the given depth and data width, and the given name and prefix.
  */
@@ -127,7 +160,7 @@ implicit_memory* create_implicit_memory_block(int data_width, long memory_depth,
     // Create a fake ast node.
     node->related_ast_node = create_node_w_type(RAM, node->loc);
     node->related_ast_node->children = (ast_node_t**)vtr::calloc(1, sizeof(ast_node_t*));
-    node->related_ast_node->identifier_node = create_tree_node_id(vtr::strdup(DUAL_PORT_RAM_string), loc);
+    node->related_ast_node->identifier_node = create_tree_node_id(vtr::strdup(SINGLE_PORT_RAM_string), loc);
 
     char* full_name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, -1);
 
@@ -182,8 +215,8 @@ implicit_memory* lookup_implicit_memory_input(char* name) {
 void register_implicit_memory_input(char* name, implicit_memory* memory) {
     if (!lookup_implicit_memory_input(name))
         implicit_memory_inputs.insert({std::string(name), memory});
-    else
-        error_message(NETLIST, memory->node->loc, "Attempted to re-register implicit memory output %s.", name);
+    // else
+    // error_message(NETLIST, memory->node->loc, "Attempted to re-register implicit memory output %s.", name);
 }
 
 /*

ODIN_II/SRC/include/implicit_memory.h

@@ -45,6 +45,7 @@ void add_output_port_to_implicit_memory(implicit_memory* memory, signal_list_t*
 implicit_memory* lookup_implicit_memory_reference_ast(char* instance_name_prefix, ast_node_t* node);
 
 char is_valid_implicit_memory_reference_ast(char* instance_name_prefix, ast_node_t* node);
+bool is_signal_list_connected_to_memory(implicit_memory* memory, signal_list_t* signals, const char* port_name);
 
 implicit_memory* create_implicit_memory_block(int data_width, long words, char* name, char* instance_name_prefix, loc_t loc);
 

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -2704,15 +2704,69 @@ signal_list_t* assignment_alias(ast_node_t* assignment, char* instance_name_pref
                 address->count = right_memory->addr_width;
             }
 
-            add_input_port_to_implicit_memory(right_memory, address, "addr1");
+            int input_pin_index = 0;
+            int output_pin_index = 0;
+            char* address_port = NULL;
+            char* output_port = NULL;
+
+            ast_node_t* right_memory_ast_node = right_memory->node->related_ast_node;
+
+            bool first_address_is_connected = is_signal_list_connected_to_memory(right_memory, address, "addr1");
+            bool second_address_is_connected = is_signal_list_connected_to_memory(right_memory, address, "addr2");
+            bool memory_is_single_port = !strcmp(right_memory_ast_node->identifier_node->types.identifier, SINGLE_PORT_RAM_string);
+
+            if (memory_is_single_port && !first_address_is_connected) {
+                if (right_memory->node->input_pins) {
+                    address_port = right_memory->node->input_pins[0]->mapping;
+
+                    if (address_port && !strcmp(address_port, "addr1")) {
+                        // changing to a dual-port ram, since the first port is already connected
+                        ast_node_t* identifier_node = create_tree_node_id(vtr::strdup(DUAL_PORT_RAM_string), assignment->loc);
+
+                        // free the default identifier node (spram)
+                        if (right_memory_ast_node->identifier_node) {
+                            free_single_node(right_memory_ast_node->identifier_node);
+                        }
+
+                        right_memory_ast_node->identifier_node = identifier_node;
+
+                        input_pin_index = right_memory->data_width + right_memory->data_width + right_memory->addr_width + 2;
+                        output_pin_index = right_memory->data_width;
+
+                        // first address port is already been used, so that the second port should use for the next address port
+                        address_port = vtr::strdup("addr2");
+                        output_port = vtr::strdup("out2");
+                    }
+
+                } else {
+                    address_port = vtr::strdup("addr1");
+                    output_port = vtr::strdup("out1");
+                }
+
+                add_input_port_to_implicit_memory(right_memory, address, address_port);
+
+            } else if (!memory_is_single_port && second_address_is_connected) {
+                input_pin_index = right_memory->data_width + right_memory->data_width + right_memory->addr_width + 2;
+                output_pin_index = right_memory->data_width;
+
+                address_port = vtr::strdup("addr2");
+                output_port = vtr::strdup("out2");
+
+            } else if (first_address_is_connected) {
+                address_port = vtr::strdup("addr1");
+                output_port = vtr::strdup("out1");
+            }
+
             // Right inputs are the inputs to the memory. This will contain the address only.
             right_inputs = init_signal_list();
             char* name = right->identifier_node->types.identifier;
-            for (int i = 0; i < address->count; i++) {
+
+            int i;
+            for (i = 0; i < address->count; i++) {
                 npin_t* pin = address->pins[i];
                 if (pin->name)
                     vtr::free(pin->name);
-                pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, i);
+                pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, input_pin_index + i);
                 add_pin_to_signal_list(right_inputs, pin);
             }
             free_signal_list(address);
@@ -2721,19 +2775,22 @@ signal_list_t* assignment_alias(ast_node_t* assignment, char* instance_name_pref
             // treated the same as the outputs from the RHS of any assignment.
             right_outputs = init_signal_list();
             signal_list_t* outputs = init_signal_list();
-            for (int i = 0; i < right_memory->data_width; i++) {
+            for (i = output_pin_index; i < right_memory->data_width + output_pin_index; i++) {
                 npin_t* pin = allocate_npin();
                 add_pin_to_signal_list(outputs, pin);
-                pin->name = make_full_ref_name("", NULL, NULL, right_memory->node->name, i);
+                pin->name = make_full_ref_name(right_memory->node->name, NULL, NULL, output_port, i - output_pin_index);
                 nnet_t* net = allocate_nnet();
                 add_driver_pin_to_net(net, pin);
                 pin = allocate_npin();
                 add_fanout_pin_to_net(net, pin);
                 //right_outputs->pins[i] = pin;
                 add_pin_to_signal_list(right_outputs, pin);
             }
-            add_output_port_to_implicit_memory(right_memory, outputs, "out1");
+            add_output_port_to_implicit_memory(right_memory, outputs, output_port);
             free_signal_list(outputs);
+
+            vtr::free(address_port);
+            vtr::free(output_port);
         }
 
     } else {
@@ -2783,36 +2840,90 @@ signal_list_t* assignment_alias(ast_node_t* assignment, char* instance_name_pref
                     address->count = left_memory->addr_width;
                 }
 
-                add_input_port_to_implicit_memory(left_memory, address, "addr2");
-
                 signal_list_t* data;
                 if (right_memory)
                     data = right_outputs;
                 else
                     data = in_1;
 
+                int input_pin_index = 0;
+                char* address_port = NULL;
+                char* data_port = NULL;
+                char* we_port = NULL;
+
+                ast_node_t* left_memory_ast_node = left_memory->node->related_ast_node;
+
+                bool first_address_is_connected = is_signal_list_connected_to_memory(left_memory, address, "addr1");
+                bool second_address_is_connected = is_signal_list_connected_to_memory(left_memory, address, "addr2");
+                bool memory_is_single_port = !strcmp(left_memory_ast_node->identifier_node->types.identifier, SINGLE_PORT_RAM_string);
+
+                if (memory_is_single_port && !first_address_is_connected) {
+                    if (left_memory->node->input_pins) {
+                        address_port = left_memory->node->input_pins[0]->mapping;
+
+                        if (address_port && !strcmp(address_port, "addr1")) {
+                            // changing to a dual-port ram, since the first port is already connected
+                            ast_node_t* identifier_node = create_tree_node_id(vtr::strdup(DUAL_PORT_RAM_string), assignment->loc);
+
+                            // free the default identifier node (spram)
+                            if (left_memory_ast_node->identifier_node) {
+                                free_single_node(left_memory_ast_node->identifier_node);
+                            }
+
+                            left_memory_ast_node->identifier_node = identifier_node;
+
+                            input_pin_index = left_memory->data_width + left_memory->data_width + left_memory->addr_width + 2;
+
+                            // first address port is already been used, so that the second port should use for the next address port
+                            address_port = vtr::strdup("addr2");
+                            data_port = vtr::strdup("data2");
+                            we_port = vtr::strdup("we2");
+                        }
+
+                    } else {
+                        address_port = vtr::strdup("addr1");
+                        data_port = vtr::strdup("data1");
+                        we_port = vtr::strdup("we1");
+                    }
+
+                    add_input_port_to_implicit_memory(left_memory, address, address_port);
+
+                } else if (!memory_is_single_port && second_address_is_connected) {
+                    input_pin_index = left_memory->data_width + left_memory->data_width + left_memory->addr_width + 2;
+
+                    // first address port is already been used, so that the second port should use for the next address port
+                    address_port = vtr::strdup("addr2");
+                    data_port = vtr::strdup("data2");
+                    we_port = vtr::strdup("we2");
+
+                } else if (first_address_is_connected) {
+                    address_port = vtr::strdup("addr1");
+                    data_port = vtr::strdup("data1");
+                    we_port = vtr::strdup("we1");
+                }
+
                 // Pad/shrink the data to the width of the memory.
                 if (data) {
                     while (data->count < left_memory->data_width)
                         add_pin_to_signal_list(data, get_zero_pin(verilog_netlist));
 
                     data->count = left_memory->data_width;
 
-                    add_input_port_to_implicit_memory(left_memory, data, "data2");
+                    add_input_port_to_implicit_memory(left_memory, data, data_port);
 
                     signal_list_t* we = init_signal_list();
                     add_pin_to_signal_list(we, get_one_pin(verilog_netlist));
-                    add_input_port_to_implicit_memory(left_memory, we, "we2");
+                    add_input_port_to_implicit_memory(left_memory, we, we_port);
 
                     in_1 = init_signal_list();
                     char* name = left->identifier_node->types.identifier;
+
                     int i;
-                    int pin_index = left_memory->data_width + left_memory->data_width + left_memory->addr_width + 2;
                     for (i = 0; i < address->count; i++) {
                         npin_t* pin = address->pins[i];
                         if (pin->name)
                             vtr::free(pin->name);
-                        pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, pin_index++);
+                        pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, input_pin_index++);
                         add_pin_to_signal_list(in_1, pin);
                     }
                     free_signal_list(address);
@@ -2821,7 +2932,7 @@ signal_list_t* assignment_alias(ast_node_t* assignment, char* instance_name_pref
                         npin_t* pin = data->pins[i];
                         if (pin->name)
                             vtr::free(pin->name);
-                        pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, pin_index++);
+                        pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, input_pin_index++);
                         add_pin_to_signal_list(in_1, pin);
                     }
                     free_signal_list(data);
@@ -2830,13 +2941,17 @@ signal_list_t* assignment_alias(ast_node_t* assignment, char* instance_name_pref
                         npin_t* pin = we->pins[i];
                         if (pin->name)
                             vtr::free(pin->name);
-                        pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, pin_index++);
+                        pin->name = make_full_ref_name(instance_name_prefix, NULL, NULL, name, input_pin_index++);
                         add_pin_to_signal_list(in_1, pin);
                     }
                     free_signal_list(we);
 
                     out_list = NULL;
                 }
+
+                vtr::free(address_port);
+                vtr::free(data_port);
+                vtr::free(we_port);
             }
         }
     } else {

ODIN_II/SRC/netlist_utils.cpp

@@ -589,7 +589,15 @@ signal_list_t* combine_lists(signal_list_t** signal_lists, int num_signal_lists)
         if (signal_lists[i]) {
             int j;
             for (j = 0; j < signal_lists[i]->count; j++) {
-                add_pin_to_signal_list(signal_lists[0], signal_lists[i]->pins[j]);
+                int k;
+                bool pin_already_added = false;
+                for (k = 0; k < signal_lists[0]->count; k++) {
+                    if (!strcmp(signal_lists[0]->pins[k]->name, signal_lists[i]->pins[j]->name))
+                        pin_already_added = true;
+                }
+
+                if (!pin_already_added)
+                    add_pin_to_signal_list(signal_lists[0], signal_lists[i]->pins[j]);
             }
 
             free_signal_list(signal_lists[i]);

ODIN_II/regression_test/benchmark/task/large/synthesis_result.json

@@ -1232,6 +1232,18 @@
         "Estimated LUTs": 209209,
         "Total Node": 295165
     },
+    "large/matmul_8x8_fp16/k6_frac_N10_frac_chain_mem32K_40nm": {
+        "test_name": "large/matmul_8x8_fp16/k6_frac_N10_frac_chain_mem32K_40nm",
+        "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
+        "verilog": "matmul_8x8_fp16.v",
+        "exit": 134,
+        "errors": [
+            "matmul_8x8_fp16.v:1648:1 [AST] Can't find module name mac_fp"
+        ],
+        "warnings": [
+            "matmul_8x8_fp16.v:1212:7 [AST] Odin does not handle signed REG (counter)"
+        ]
+    },
     "DEFAULT": {
         "test_name": "n/a",
         "architecture": "n/a",

ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json

@@ -1057,7 +1057,7 @@
         "simulation_time(ms)": 216.7,
         "test_coverage(%)": 100,
         "Latch Drivers": 1,
-        "Pi": 35,
+        "Pi": 70,
         "Po": 32,
         "logic element": 32,
         "latch": 32,
@@ -1076,7 +1076,7 @@
         "simulation_time(ms)": 23,
         "test_coverage(%)": 88.9,
         "Latch Drivers": 1,
-        "Pi": 35,
+        "Pi": 70,
         "Po": 32,
         "logic element": 878,
         "latch": 288,

ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json

@@ -1289,7 +1289,7 @@
         "exec_time(ms)": 61.1,
         "synthesis_time(ms)": 15,
         "Latch Drivers": 1,
-        "Pi": 35,
+        "Pi": 70,
         "Po": 32,
         "latch": 32,
         "Adder": 0,
@@ -1307,7 +1307,7 @@
         "exec_time(ms)": 23.6,
         "synthesis_time(ms)": 22.2,
         "Latch Drivers": 1,
-        "Pi": 35,
+        "Pi": 70,
         "Po": 32,
         "logic element": 846,
         "latch": 288,