vpr: print route now takes the correct blkid based on subtile loc

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/physical_types.cpp

@@ -111,6 +111,24 @@ std::vector<int> t_physical_tile_type::get_clock_pins_indices() const {
     return this->clock_pin_indices;
 }
 
+int t_physical_tile_type::get_sub_tile_loc_from_pin(int pin_num) const {
+    VTR_ASSERT(pin_num < this->num_pins);
+
+    for (auto sub_tile : this->sub_tiles) {
+        auto max_inst_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
+
+        for (int pin = 0; pin < sub_tile.num_phy_pins; pin++) {
+            if (sub_tile.sub_tile_to_tile_pin_indices[pin] == pin_num) {
+                //If the physical tile pin matches pin_num, return the
+                //corresponding absolute capacity location of the sub_tile
+                return pin / max_inst_pins + sub_tile.capacity.low;
+            }
+        }
+    }
+
+    return OPEN;
+}
+
 /**
  * t_pb_graph_node
  */

libs/libarchfpga/src/physical_types.h

@@ -624,6 +624,8 @@ struct t_physical_tile_type {
     /* Returns the indices of pins that contain a clock for this physical logic block */
     std::vector<int> get_clock_pins_indices() const;
 
+    int get_sub_tile_loc_from_pin(int pin_num) const;
+
     // TODO: Remove is_input_type / is_output_type as part of
     // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193
 

vpr/src/route/route_common.cpp

@@ -1278,11 +1278,14 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
 
                     fprintf(fp, "%d  ", device_ctx.rr_nodes[inode].ptc_num());
 
-                    if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) {
+                    auto physical_tile = device_ctx.grid[ilow][jlow].type;
+                    if (!is_io_type(physical_tile) && (rr_type == IPIN || rr_type == OPIN)) {
                         int pin_num = device_ctx.rr_nodes[inode].ptc_num();
                         int xoffset = device_ctx.grid[ilow][jlow].width_offset;
                         int yoffset = device_ctx.grid[ilow][jlow].height_offset;
-                        ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[0];
+                        int sub_tile_offset = physical_tile->get_sub_tile_loc_from_pin(pin_num);
+
+                        ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[sub_tile_offset];
                         VTR_ASSERT(iblock);
                         t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num);
                         t_pb_type* pb_type = pb_pin->parent_node->pb_type;

vpr/src/util/vpr_utils.h

@@ -30,7 +30,7 @@ bool is_empty_type(t_logical_block_type_ptr type);
 //Returns the corresponding physical type given the logical type as parameter
 t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk);
 
-//Retyrbs the sub tile corresponding to the logical block location within a physical type
+//Returns the sub tile corresponding to the logical block location within a physical type
 int get_sub_tile_index(ClusterBlockId blk);
 
 int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node);