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23 | 23 | enum class e_rr_type : unsigned char {
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24 | 24 | SOURCE = 0, ///<A dummy node that is a logical output within a block -- i.e., the gate that generates a signal.
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25 | 25 | SINK, ///<A dummy node that is a logical input within a block -- i.e. the gate that needs a signal.
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26 |
| - IPIN, ///Input pin to a block |
27 |
| - OPIN, ///Output pin of a block |
28 |
| - CHANX, ///x-directed routing wire, or an x-directed segment of a channel for global routing |
29 |
| - CHANY, ///y-directed routing wire, or a y-directed segment of a channel for global routing |
| 26 | + IPIN, ///<Input pin to a block |
| 27 | + OPIN, ///<Output pin of a block |
| 28 | + CHANX, ///<x-directed routing wire, or an x-directed segment of a channel for global routing |
| 29 | + CHANY, ///<y-directed routing wire, or a y-directed segment of a channel for global routing |
30 | 30 | NUM_RR_TYPES
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31 | 31 | };
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32 | 32 |
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33 | 33 | constexpr std::array<e_rr_type, (size_t)e_rr_type::NUM_RR_TYPES> RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN,
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34 | 34 | e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY}};
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35 | 35 | constexpr std::array<const char*, (size_t)e_rr_type::NUM_RR_TYPES> rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}};
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36 | 36 |
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37 |
| -/* |
38 |
| - * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. |
39 |
| - * Direction::DEC: wire_driver is positioned at the high-coordinate end of the wire. |
40 |
| - * Direction::BIDIR: wire has multiple drivers, so signals can travel either way along the wire |
41 |
| - * Direction::NONE: node does not have a direction, such as IPIN/OPIN |
| 37 | +/** |
| 38 | + * @enum Direction |
| 39 | + * @brief Represents the wire direction for a routing resource node. |
42 | 40 | */
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43 | 41 | enum class Direction : unsigned char {
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44 |
| - INC = 0, |
45 |
| - DEC = 1, |
46 |
| - BIDIR = 2, |
47 |
| - NONE = 3, |
| 42 | + INC = 0, ///< wire driver is positioned at the low-coordinate end of the wire. |
| 43 | + DEC = 1, ///< wire_driver is positioned at the high-coordinate end of the wire. |
| 44 | + BIDIR = 2, ///< wire has multiple drivers, so signals can travel either way along the wire |
| 45 | + NONE = 3, ///< node does not have a direction, such as IPIN/OPIN |
48 | 46 | NUM_DIRECTIONS
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49 | 47 | };
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50 | 48 |
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| 49 | + |
51 | 50 | constexpr std::array<const char*, static_cast<int>(Direction::NUM_DIRECTIONS)> DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NONE"}};
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52 | 51 |
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53 | 52 | //this array is used in rr_graph_storage.cpp so that node_direction_string() can return a const std::string&
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