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Merge pull request #1890 from sdamghan/make_yosys_odin
Yosys+Odin-II's new makefile options
2 parents 0994698 + a066d98 commit a517b70

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3 files changed

+56
-17
lines changed

3 files changed

+56
-17
lines changed

ODIN_II/Makefile

Lines changed: 50 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,18 @@
11
ODIN_ROOT=$(PWD)
22
NB_OF_PROCESS ?= $(shell /usr/bin/env python3 -c "import multiprocessing; print(multiprocessing.cpu_count())")
33

4+
# handling elaborator name
5+
ifdef ELABORATOR
6+
_ELABORATOR=$(shell echo $(ELABORATOR) | tr '[:lower:]' '[:upper:]')
7+
else
8+
_ELABORATOR=ODIN
9+
endif
10+
11+
# Yosys+Odin-II compile flags
12+
ifeq ($(_ELABORATOR), YOSYS)
13+
_YOSYS_COMPILE_FLAG="-DODIN_USE_YOSYS=ON"
14+
endif
15+
416
################
517
# build with ninja when doable
618
################
@@ -57,33 +69,29 @@ $(ODIN_BUILD_DIR)/.%.build: _init
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5870
_set_build: $(ODIN_BUILD_DIR)/.regular.build
5971
cd $(BUILD_DIR) &&\
60-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) ..
72+
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) $(_YOSYS_COMPILE_FLAG) ..
6173

6274
_set_debug: $(ODIN_BUILD_DIR)/.debug.build
6375
cd $(BUILD_DIR) &&\
64-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) -DODIN_DEBUG=on ..
76+
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) $(_YOSYS_COMPILE_FLAG) -DODIN_DEBUG=on ..
6577

6678
_set_warn: $(ODIN_BUILD_DIR)/.warn.build
6779
cd $(BUILD_DIR) &&\
68-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) -DODIN_WARN=on ..
80+
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) $(_YOSYS_COMPILE_FLAG) -DODIN_WARN=on ..
6981

7082
_set_gcov: $(ODIN_BUILD_DIR)/.gcov.build
7183
cd $(BUILD_DIR) &&\
72-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) -DODIN_COVERAGE=on ..
84+
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) $(_YOSYS_COMPILE_FLAG) -DODIN_COVERAGE=on ..
7385

7486
_set_clang_tidy: $(ODIN_BUILD_DIR)/.tidy.build
7587
cd $(BUILD_DIR) &&\
76-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) -DODIN_TIDY=on ..
88+
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) $(_YOSYS_COMPILE_FLAG) -DODIN_TIDY=on ..
7789

7890
_set_sanitize: $(ODIN_BUILD_DIR)/.sanitize.build
7991
cd $(BUILD_DIR) &&\
80-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) -DODIN_SANITIZE=on ..
92+
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) $(_YOSYS_COMPILE_FLAG) -DODIN_SANITIZE=on ..
8193

82-
_set_yosys+odin: $(ODIN_BUILD_DIR)/.yosys+odin.build
83-
cd $(BUILD_DIR) &&\
84-
cmake $(CMAKE_GEN_ARGS) $(CMAKE_ARGS) -DODIN_USE_YOSYS=ON ..
85-
86-
BUILD_IT_TARGETS = build debug warn gcov clang_tidy sanitize yosys+odin
94+
BUILD_IT_TARGETS = build debug warn gcov clang_tidy sanitize
8795
$(foreach t,$(BUILD_IT_TARGETS), $(eval $(call _build_it_gen,$(t))))
8896

8997
scrub:
@@ -105,17 +113,27 @@ test_coverage:
105113
$(MAKE) gcovr
106114

107115
test:
116+
ifeq ($(_ELABORATOR), ODIN)
108117
$(MAKE) sanitize \
109118
&& ./verify_odin.sh --no_report -j $(NB_OF_PROCESS) \
110119
-t regression_test/benchmark/suite/light_suite \
111120
-t regression_test/benchmark/suite/vtr_light_suite \
112121
&& $(MAKE) build \
113122
&& ./verify_odin.sh --no_report --continue -j $(NB_OF_PROCESS) \
114123
-t regression_test/benchmark/suite/heavy_suite; \
115-
./verify_odin.sh --status_only
116-
124+
./verify_odin.sh --status_only
125+
else ifeq ($(_ELABORATOR), YOSYS)
126+
$(MAKE) sanitize ELABORATOR=YOSYS \
127+
&& ./verify_odin.sh --no_report -j $(NB_OF_PROCESS) \
128+
-t regression_test/benchmark/suite/yosys+odin/techmap_lightsuite \
129+
&& $(MAKE) build ELABORATOR=YOSYS \
130+
&& ./verify_odin.sh --no_report --continue -j $(NB_OF_PROCESS) \
131+
-t regression_test/benchmark/suite/yosys+odin/techmap_heavysuite; \
132+
./verify_odin.sh --status_only
133+
endif
117134

118135
generate_expectation:
136+
ifeq ($(_ELABORATOR), ODIN)
119137
$(MAKE) sanitize \
120138
&& ./verify_odin.sh --$@ --no_report -j $(NB_OF_PROCESS) \
121139
-t regression_test/benchmark/suite/light_suite \
@@ -124,8 +142,18 @@ generate_expectation:
124142
&& ./verify_odin.sh --$@ --no_report --continue -j $(NB_OF_PROCESS) \
125143
-t regression_test/benchmark/suite/heavy_suite; \
126144
./verify_odin.sh --status_only
145+
else ifeq ($(_ELABORATOR), YOSYS)
146+
$(MAKE) sanitize ELABORATOR=YOSYS \
147+
&& ./verify_odin.sh --$@ --no_report -j $(NB_OF_PROCESS) \
148+
-t regression_test/benchmark/suite/yosys+odin/techmap_lightsuite \
149+
$(MAKE) build ELABORATOR=YOSYS \
150+
&& ./verify_odin.sh --$@ --no_report --continue -j $(NB_OF_PROCESS) \
151+
-t regression_test/benchmark/suite/yosys+odin/techmap_heavysuite; \
152+
./verify_odin.sh --status_only
153+
endif
127154

128155
regenerate_expectation:
156+
ifeq ($(_ELABORATOR), ODIN)
129157
$(MAKE) sanitize \
130158
&& ./verify_odin.sh --$@ --no_report -j $(NB_OF_PROCESS) \
131159
-t regression_test/benchmark/suite/light_suite \
@@ -134,3 +162,12 @@ regenerate_expectation:
134162
&& ./verify_odin.sh --$@ --no_report --continue -j $(NB_OF_PROCESS) \
135163
-t regression_test/benchmark/suite/heavy_suite; \
136164
./verify_odin.sh --status_only
165+
else ifeq ($(_ELABORATOR), YOSYS)
166+
$(MAKE) sanitize ELABORATOR=YOSYS \
167+
&& ./verify_odin.sh --$@ --no_report -j $(NB_OF_PROCESS) \
168+
-t regression_test/benchmark/suite/yosys+odin/techmap_lightsuite \
169+
$(MAKE) build ELABORATOR=YOSYS \
170+
&& ./verify_odin.sh --$@ --no_report --continue -j $(NB_OF_PROCESS) \
171+
-t regression_test/benchmark/suite/yosys+odin/techmap_heavysuite; \
172+
./verify_odin.sh --status_only
173+
endif

ODIN_II/regression_test/tools/run_yosys.sh

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ RED=$'\033[31;1m'
3939
NC=$'\033[0m' # No Color
4040

4141
# defaults
42-
_YOSYS_EXEC="yosys"
42+
_YOSYS_EXEC="${VTR_DIR}/libs/EXTERNAL/libyosys/yosys"
4343
_TEST_INPUT_LIST=()
4444
_VERILOG_INPUT_LIST=()
4545
_REGENERATE_BLIF="off"

ODIN_II/regression_test/tools/synth.tcl

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ yosys -import
44
# Feel free to specify file paths using "$env(VTR_ROOT)/ ..."
55

66
# Read the hardware decription Verilog
7-
read_verilog -nomem2reg -nolatches $env(VTR_ROOT)/ODIN_II/regression_test/benchmark/verilog/common/mux.v;
7+
read_verilog -nomem2reg -nolatches $env(TCL_CIRCUIT);
88
# Check that cells match libraries and find top module
99
hierarchy -check -auto-top;
1010

@@ -20,8 +20,8 @@ memory_collect; memory_dff; opt;
2020
# Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
2121
check;
2222
# resolve asynchronous dffs
23-
techmap -map $env(VTR_ROOT)/ODIN_II/techlib/adff2dff.v;
24-
techmap -map $env(VTR_ROOT)/ODIN_II/techlib/adffe2dff.v;
23+
techmap -map $env(ODIN_TECHLIB)/adff2dff.v;
24+
techmap -map $env(ODIN_TECHLIB)/adffe2dff.v;
2525
# convert mem block to bram/rom
2626

2727
# [NOTE]: Yosys complains about expression width more than 24 bits.
@@ -40,3 +40,5 @@ opt -undriven -full; # -noff #potential option to remove all sdff and etc. Only
4040
autoname;
4141
# Print statistics
4242
stat;
43+
44+
write_blif -param -impltf $env(TCL_BLIF);

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