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updated the task list and the golden results
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
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stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 718.56 vpr 1.17 GiB 42 752 0 0 0 0 success v8.0.0-11407-ge3caf5734-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T09:25:25 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 1226276 13 29 26295 20086 1 12536 794 40 32 1280 -1 EP4SGX110 1069.2 MiB 101.75 72218 243344 47160 189629 6555 1197.5 MiB 158.76 2.25 5.46034 -5303.17 -4.46034 2.83892 0.45 0.732754 0.54291 51.3033 38.3927 83501 6.66196 19920 1.58928 28207 39603 32076664 2698324 0 0 2.34711e+07 18336.8 16 375646 4005745 -1 5.52802 2.66399 -5393.44 -4.52802 0 0 102.52 -1 -1 1197.5 MiB 68.66 80.5763 62.6799 1197.5 MiB -1 186.82
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stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 63.24 vpr 1.16 GiB 42 752 0 0 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 1220852 13 29 26295 20086 1 12536 794 40 32 1280 -1 EP4SGX110 1063.7 MiB 13.82 72218 243344 47160 189629 6555 1192.2 MiB 7.72 0.11 5.46034 -5303.17 -4.46034 2.83892 0.01 0.020645 0.0170889 1.61051 1.32621 83501 6.66196 19920 1.58928 28207 39603 32076664 2698324 0 0 2.34711e+07 18336.8 16 375646 4005745 -1 5.52802 2.66399 -5393.44 -4.52802 0 0 6.91 -1 -1 1192.2 MiB 4.16 2.86687 2.4502 1192.2 MiB -1 13.03

vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

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regression_tests/vtr_reg_strong/strong_custom_grid
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regression_tests/vtr_reg_strong/strong_custom_pin_locs
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regression_tests/vtr_reg_strong/strong_custom_switch_block
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regression_tests/vtr_reg_strong/starting_custom_SB_loc
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regression_tests/vtr_reg_strong/strong_custom_sb_loc
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regression_tests/vtr_reg_strong/strong_dedicated_clock
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regression_tests/vtr_reg_strong/strong_default_fc_pinlocs
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regression_tests/vtr_reg_strong/strong_depop

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