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jeanlegoemacdo12
jeanlego
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emacdo12
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ast_util.cpp: Fixed possible memory leak c_simple_print. When checking for octal number, it checks that there are enough characters first. Also, added a line to check for indexing case where the (#1393)
index is the same as start which prints the whole line the function (for some reason). Co-authored-by: emacdo12 <[email protected]>
2 parents 366d5cc + 21aeca5 commit 9ff7158

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9 files changed

+319
-423
lines changed

9 files changed

+319
-423
lines changed

‎ODIN_II/SRC/ast_util.cpp

Lines changed: 37 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1338,39 +1338,52 @@ void assert_constant_positionnal_args(ast_node_t* node, long arg_count) {
13381338
* a simple printf would not be able to do this since escaped characters are compile time
13391339
*/
13401340
void c_simple_print(std::string str) {
1341+
size_t str_size = str.size();
13411342
size_t start = 0;
13421343
while (start != std::string::npos) {
13431344
size_t format_char_index = str.find_first_of('\\', start);
13441345
size_t next_char = format_char_index;
1345-
printf("%s", str.substr(start, format_char_index).c_str());
1346+
if (start != format_char_index) {
1347+
printf("%s", str.substr(start, format_char_index).c_str());
1348+
}
13461349
// print the string
13471350
if (format_char_index != std::string::npos) {
1348-
// try and see if its an octal number
1349-
char buffer[4] = {
1350-
str[format_char_index + 1],
1351-
str[format_char_index + 2],
1352-
str[format_char_index + 3],
1353-
0};
1354-
next_char = format_char_index + 4;
1355-
char* endptr = NULL;
1356-
char octal_value = (char)strtoul(buffer, &endptr, 8);
1357-
if (endptr == &buffer[3]) {
1358-
// if it is an octal number print the octal char
1359-
printf("%c", octal_value);
1360-
} else {
1361-
next_char = format_char_index + 2;
1362-
switch (str[format_char_index + 1]) {
1363-
case 'n':
1364-
printf("\n");
1365-
break;
1366-
case 't':
1367-
printf("\t");
1368-
break;
1369-
default:
1351+
next_char = format_char_index + 2;
1352+
switch (str[format_char_index + 1]) {
1353+
case 'n':
1354+
printf("\n");
1355+
break;
1356+
case 't':
1357+
printf("\t");
1358+
break;
1359+
default:
1360+
// can only be octal if there is 3+ chars following
1361+
if ((str_size - 3) >= format_char_index) {
1362+
// try and see if its an octal number
1363+
char buffer[4] = {
1364+
str[format_char_index + 1],
1365+
str[format_char_index + 2],
1366+
str[format_char_index + 3],
1367+
0};
1368+
next_char = format_char_index + 4;
1369+
char* endptr = NULL;
1370+
char octal_value = (char)strtoul(buffer, &endptr, 8);
1371+
if (endptr == &buffer[3]) {
1372+
// if it is an octal number print the octal char
1373+
printf("%c", octal_value);
1374+
} else {
1375+
// otherwise just print the character
1376+
next_char = format_char_index + 2;
1377+
printf("%c", str[format_char_index + 1]);
1378+
break;
1379+
}
1380+
1381+
} else {
13701382
// otherwise just print the character
1383+
next_char = format_char_index + 2;
13711384
printf("%c", str[format_char_index + 1]);
13721385
break;
1373-
}
1386+
}
13741387
}
13751388
}
13761389
start = next_char;

‎ODIN_II/regression_test/benchmark/task/test/simulation_result.json

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
{
2+
"test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm": {
3+
"test_name": "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm",
4+
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
5+
"blif": "ifdef_undefined.blif",
6+
"exit": 134,
7+
"errors": [
8+
"OUTPUT_BLIF Vector files differ."
9+
],
10+
"warnings": [
11+
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
12+
],
13+
"max_rss(MiB)": -1,
14+
"exec_time(ms)": -1,
15+
"simulation_time(ms)": -1,
16+
"test_coverage(%)": -1,
17+
"Latch Drivers": -1,
18+
"Pi": -1,
19+
"Po": -1,
20+
"logic element": -1,
21+
"latch": -1,
22+
"Adder": -1,
23+
"Multiplier": -1,
24+
"Memory": -1,
25+
"Hard Ip": -1,
26+
"generic logic size": 4,
27+
"Longest Path": -1,
28+
"Average Path": -1,
29+
"Estimated LUTs": -1,
30+
"Total Node": -1
31+
},
32+
"test/ifdef_undefined/k6_N10_40nm": {
33+
"test_name": "test/ifdef_undefined/k6_N10_40nm",
34+
"architecture": "k6_N10_40nm.xml",
35+
"blif": "ifdef_undefined.blif",
36+
"exit": 134,
37+
"errors": [
38+
"OUTPUT_BLIF Vector files differ."
39+
],
40+
"warnings": [
41+
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
42+
],
43+
"max_rss(MiB)": -1,
44+
"exec_time(ms)": -1,
45+
"simulation_time(ms)": -1,
46+
"test_coverage(%)": -1,
47+
"Latch Drivers": -1,
48+
"Pi": -1,
49+
"Po": -1,
50+
"logic element": -1,
51+
"latch": -1,
52+
"Adder": -1,
53+
"Multiplier": -1,
54+
"Memory": -1,
55+
"Hard Ip": -1,
56+
"generic logic size": 6,
57+
"Longest Path": -1,
58+
"Average Path": -1,
59+
"Estimated LUTs": -1,
60+
"Total Node": -1
61+
},
62+
"test/ifdef_undefined/k6_N10_mem32K_40nm": {
63+
"test_name": "test/ifdef_undefined/k6_N10_mem32K_40nm",
64+
"architecture": "k6_N10_mem32K_40nm.xml",
65+
"blif": "ifdef_undefined.blif",
66+
"exit": 134,
67+
"errors": [
68+
"OUTPUT_BLIF Vector files differ."
69+
],
70+
"warnings": [
71+
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
72+
],
73+
"max_rss(MiB)": -1,
74+
"exec_time(ms)": -1,
75+
"simulation_time(ms)": -1,
76+
"test_coverage(%)": -1,
77+
"Latch Drivers": -1,
78+
"Pi": -1,
79+
"Po": -1,
80+
"logic element": -1,
81+
"latch": -1,
82+
"Adder": -1,
83+
"Multiplier": -1,
84+
"Memory": -1,
85+
"Hard Ip": -1,
86+
"generic logic size": 6,
87+
"Longest Path": -1,
88+
"Average Path": -1,
89+
"Estimated LUTs": -1,
90+
"Total Node": -1
91+
},
92+
"test/ifdef_undefined/no_arch": {
93+
"test_name": "test/ifdef_undefined/no_arch",
94+
"architecture": "n/a",
95+
"blif": "ifdef_undefined.blif",
96+
"exit": 134,
97+
"errors": [
98+
"OUTPUT_BLIF Vector files differ."
99+
],
100+
"warnings": [
101+
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
102+
],
103+
"max_rss(MiB)": -1,
104+
"exec_time(ms)": -1,
105+
"simulation_time(ms)": -1,
106+
"test_coverage(%)": -1,
107+
"Latch Drivers": -1,
108+
"Pi": -1,
109+
"Po": -1,
110+
"logic element": -1,
111+
"latch": -1,
112+
"Adder": -1,
113+
"Multiplier": -1,
114+
"Memory": -1,
115+
"Hard Ip": -1,
116+
"generic logic size": -1,
117+
"Longest Path": -1,
118+
"Average Path": -1,
119+
"Estimated LUTs": -1,
120+
"Total Node": -1
121+
}
122+
}

‎ODIN_II/regression_test/benchmark/task/test/synthesis_result.json

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
{
2+
"test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm": {
3+
"test_name": "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm",
4+
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
5+
"verilog": "ifdef_undefined.v",
6+
"exit": 0,
7+
"errors": [],
8+
"warnings": [
9+
"OUTPUT_BLIF want to see if this will print json",
10+
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
11+
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
12+
],
13+
"max_rss(MiB)": 32.8,
14+
"exec_time(ms)": 71.3,
15+
"synthesis_time(ms)": 0.7,
16+
"Latch Drivers": 0,
17+
"Pi": 0,
18+
"Po": 1,
19+
"logic element": 0,
20+
"latch": 0,
21+
"Adder": 0,
22+
"Multiplier": 0,
23+
"Memory": 0,
24+
"Hard Ip": -1,
25+
"generic logic size": 4,
26+
"Longest Path": 1,
27+
"Average Path": 1,
28+
"Estimated LUTs": 0,
29+
"Total Node": 0
30+
},
31+
"test/ifdef_undefined/k6_N10_40nm": {
32+
"test_name": "test/ifdef_undefined/k6_N10_40nm",
33+
"architecture": "k6_N10_40nm.xml",
34+
"verilog": "ifdef_undefined.v",
35+
"exit": 0,
36+
"errors": [],
37+
"warnings": [
38+
"OUTPUT_BLIF want to see if this will print json",
39+
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
40+
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
41+
],
42+
"max_rss(MiB)": 15.1,
43+
"exec_time(ms)": 11,
44+
"synthesis_time(ms)": 0.9,
45+
"Latch Drivers": 0,
46+
"Pi": 0,
47+
"Po": 1,
48+
"logic element": 0,
49+
"latch": 0,
50+
"Adder": -1,
51+
"Multiplier": -1,
52+
"Memory": -1,
53+
"Hard Ip": -1,
54+
"generic logic size": 6,
55+
"Longest Path": 1,
56+
"Average Path": 1,
57+
"Estimated LUTs": 0,
58+
"Total Node": 0
59+
},
60+
"test/ifdef_undefined/k6_N10_mem32K_40nm": {
61+
"test_name": "test/ifdef_undefined/k6_N10_mem32K_40nm",
62+
"architecture": "k6_N10_mem32K_40nm.xml",
63+
"verilog": "ifdef_undefined.v",
64+
"exit": 0,
65+
"errors": [],
66+
"warnings": [
67+
"OUTPUT_BLIF want to see if this will print json",
68+
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
69+
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
70+
],
71+
"max_rss(MiB)": 32.2,
72+
"exec_time(ms)": 51.1,
73+
"synthesis_time(ms)": 0.5,
74+
"Latch Drivers": 0,
75+
"Pi": 0,
76+
"Po": 1,
77+
"logic element": 0,
78+
"latch": 0,
79+
"Adder": -1,
80+
"Multiplier": 0,
81+
"Memory": 0,
82+
"Hard Ip": -1,
83+
"generic logic size": 6,
84+
"Longest Path": 1,
85+
"Average Path": 1,
86+
"Estimated LUTs": 0,
87+
"Total Node": 0
88+
},
89+
"test/ifdef_undefined/no_arch": {
90+
"test_name": "test/ifdef_undefined/no_arch",
91+
"architecture": "n/a",
92+
"verilog": "ifdef_undefined.v",
93+
"exit": 0,
94+
"errors": [],
95+
"warnings": [
96+
"OUTPUT_BLIF want to see if this will print json",
97+
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
98+
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
99+
],
100+
"max_rss(MiB)": 11.1,
101+
"exec_time(ms)": 4.6,
102+
"synthesis_time(ms)": 1.8,
103+
"Latch Drivers": 0,
104+
"Pi": 0,
105+
"Po": 1,
106+
"logic element": 0,
107+
"latch": 0,
108+
"Adder": -1,
109+
"Multiplier": -1,
110+
"Memory": -1,
111+
"Hard Ip": -1,
112+
"generic logic size": -1,
113+
"Longest Path": 1,
114+
"Average Path": 1,
115+
"Estimated LUTs": 0,
116+
"Total Node": 0
117+
}
118+
}

‎ODIN_II/regression_test/benchmark/task/test/task.conf

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
########################
2+
# operators benchmarks config
3+
########################
4+
5+
regression_params=--include_default_arch
6+
script_synthesis_params=--time_limit 3600s
7+
script_simulation_params=--time_limit 3600s
8+
simulation_params= -L reset rst -H we
9+
10+
# setup the architecture
11+
archs_dir=../vtr_flow/arch/timing
12+
13+
arch_list_add=k6_N10_40nm.xml
14+
arch_list_add=k6_N10_mem32K_40nm.xml
15+
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
16+
17+
# setup the circuits
18+
circuits_dir=regression_test/benchmark/verilog/
19+
20+
circuit_list_add=test/*.v
21+
22+
synthesis_parse_file=regression_test/parse_result/conf/synth.toml
23+
simulation_parse_file=regression_test/parse_result/conf/sim.toml

‎ODIN_II/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20_input

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -395,4 +395,4 @@ GLOBAL_SIM_BASE_CLK clk In_X
395395
0 1 0X227
396396
1 0 0X826
397397
0 0 0X255
398-
1 1 0X114
398+
1 1 0X114

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