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vpr: interchange: add device data reading
This PR adds basic support for the architecture reading: - Device - Layout - Switches Signed-off-by: Alessandro Comodi <[email protected]> Co-authored-by: Maciej Dudek <[email protected]> Co-authored-by: Alessandro Comodi <[email protected]>
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‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 283 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,72 @@ using namespace DeviceResources;
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using namespace LogicalNetlist;
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using namespace capnp;
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static float get_corner_value(Device::CornerModel::Reader model, const char* speed_model, const char* value) {
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bool slow_model = std::string(speed_model) == std::string("slow");
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bool fast_model = std::string(speed_model) == std::string("fast");
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bool min_corner = std::string(value) == std::string("min");
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bool typ_corner = std::string(value) == std::string("typ");
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bool max_corner = std::string(value) == std::string("max");
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if (!slow_model && !fast_model) {
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archfpga_throw("", __LINE__,
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"Wrong speed model `%s`. Expected `slow` or `fast`\n", speed_model);
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}
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if (!min_corner && !typ_corner && !max_corner) {
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archfpga_throw("", __LINE__,
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"Wrong corner model `%s`. Expected `min`, `typ` or `max`\n", value);
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}
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bool has_fast = model.getFast().hasFast();
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bool has_slow = model.getSlow().hasSlow();
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if (slow_model && has_slow) {
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auto half = model.getSlow().getSlow();
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if (min_corner && half.getMin().isMin()) {
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return half.getMin().getMin();
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} else if (typ_corner && half.getTyp().isTyp()) {
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return half.getTyp().getTyp();
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} else if (max_corner && half.getMax().isMax()) {
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return half.getMax().getMax();
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} else {
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if (half.getMin().isMin()) {
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return half.getMin().getMin();
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} else if (half.getTyp().isTyp()) {
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return half.getTyp().getTyp();
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} else if (half.getMax().isMax()) {
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return half.getMax().getMax();
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} else {
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archfpga_throw("", __LINE__,
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"Invalid speed model %s. No value found!\n", speed_model);
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}
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}
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} else if (fast_model && has_fast) {
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auto half = model.getFast().getFast();
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if (min_corner && half.getMin().isMin()) {
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return half.getMin().getMin();
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} else if (typ_corner && half.getTyp().isTyp()) {
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return half.getTyp().getTyp();
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} else if (max_corner && half.getMax().isMax()) {
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return half.getMax().getMax();
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} else {
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if (half.getMin().isMin()) {
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return half.getMin().getMin();
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} else if (half.getTyp().isTyp()) {
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return half.getTyp().getTyp();
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} else if (half.getMax().isMax()) {
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return half.getMax().getMax();
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} else {
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archfpga_throw("", __LINE__,
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"Invalid speed model %s. No value found!\n", speed_model);
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}
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}
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}
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return 0.;
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}
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struct ArchReader {
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public:
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ArchReader(t_arch* arch, Device::Reader& arch_reader, const char* arch_file, std::vector<t_physical_tile_type>& phys_types, std::vector<t_logical_block_type>& logical_types)
@@ -47,6 +113,11 @@ struct ArchReader {
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void read_arch() {
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process_models();
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process_device();
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process_layout();
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process_switches();
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process_segments();
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}
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private:
@@ -163,6 +234,218 @@ struct ArchReader {
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}
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}
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}
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// Layout Processing
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void process_layout() {
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auto strList = ar_.getStrList();
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auto tileList = ar_.getTileList();
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auto tileTypeList = ar_.getTileTypeList();
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t_grid_def grid_def;
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grid_def.width = grid_def.height = 0;
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for (auto tile : tileList) {
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grid_def.width = std::max(grid_def.width, tile.getCol() + 1);
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grid_def.height = std::max(grid_def.height, tile.getRow() + 1);
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}
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grid_def.grid_type = GridDefType::FIXED;
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std::string name = std::string(ar_.getName());
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if (name == "auto") {
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archfpga_throw(arch_file_, __LINE__,
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"The name auto is reserved for auto-size layouts; please choose another name");
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}
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grid_def.name = name;
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for (auto tile : tileList) {
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t_metadata_dict data;
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std::string tile_prefix(strList[tile.getName()].cStr());
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auto tileType = tileTypeList[tile.getType()];
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std::string tile_type(strList[tileType.getName()].cStr());
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size_t pos = tile_prefix.find(tile_type);
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if (pos != std::string::npos && pos == 0)
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tile_prefix.erase(pos, tile_type.length() + 1);
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data.add(arch_->strings.intern_string(vtr::string_view("fasm_prefix")),
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arch_->strings.intern_string(vtr::string_view(tile_prefix.c_str())));
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t_grid_loc_def single(tile_type, 1);
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single.x.start_expr = tile.getCol();
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single.y.start_expr = tile.getRow();
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single.x.end_expr = single.x.start_expr + " + w - 1";
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single.y.end_expr = single.y.start_expr + " + h - 1";
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single.owned_meta = std::make_unique<t_metadata_dict>(data);
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single.meta = single.owned_meta.get();
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grid_def.loc_defs.emplace_back(std::move(single));
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}
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arch_->grid_layouts.emplace_back(std::move(grid_def));
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}
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void process_device() {
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/*
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* The generic architecture data is not currently available in the interchange format
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* therefore, for a very initial implementation, the values are taken from the ones
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* used primarly in the Xilinx series7 devices, generated using SymbiFlow.
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*
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* As the interchange format develops further, with possibly more details, this function can
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* become dynamic, allowing for different parameters for the different architectures.
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*/
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arch_->R_minW_nmos = 6065.520020;
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arch_->R_minW_pmos = 18138.500000;
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arch_->grid_logic_tile_area = 14813.392;
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arch_->Chans.chan_x_dist.type = UNIFORM;
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arch_->Chans.chan_x_dist.peak = 1;
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arch_->Chans.chan_x_dist.width = 0;
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arch_->Chans.chan_x_dist.xpeak = 0;
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arch_->Chans.chan_x_dist.dc = 0;
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arch_->Chans.chan_y_dist.type = UNIFORM;
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arch_->Chans.chan_y_dist.peak = 1;
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arch_->Chans.chan_y_dist.width = 0;
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arch_->Chans.chan_y_dist.xpeak = 0;
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arch_->Chans.chan_y_dist.dc = 0;
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arch_->ipin_cblock_switch_name = std::string("generic");
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arch_->SBType = WILTON;
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arch_->Fs = 3;
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default_fc_.specified = true;
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default_fc_.in_value_type = e_fc_value_type::FRACTIONAL;
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default_fc_.in_value = 1.0;
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default_fc_.out_value_type = e_fc_value_type::FRACTIONAL;
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default_fc_.out_value = 1.0;
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}
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void process_switches() {
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std::set<std::pair<bool, uint32_t>> pip_timing_models;
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for (auto tile_type : ar_.getTileTypeList()) {
317+
for (auto pip : tile_type.getPips()) {
318+
pip_timing_models.insert(std::pair<bool, uint32_t>(pip.getBuffered21(), pip.getTiming()));
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if (!pip.getDirectional())
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pip_timing_models.insert(std::pair<bool, uint32_t>(pip.getBuffered20(), pip.getTiming()));
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}
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}
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auto timing_data = ar_.getPipTimings();
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std::vector<std::pair<bool, uint32_t>> pip_timing_models_list;
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pip_timing_models_list.reserve(pip_timing_models.size());
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for (auto entry : pip_timing_models) {
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pip_timing_models_list.push_back(entry);
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}
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auto num_switches = pip_timing_models.size() + 2;
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std::string switch_name;
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arch_->num_switches = num_switches;
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auto* switches = arch_->Switches;
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if (num_switches > 0) {
340+
switches = new t_arch_switch_inf[num_switches];
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}
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float R, Cin, Cint, Cout, Tdel;
344+
for (int i = 0; i < (int)num_switches; ++i) {
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t_arch_switch_inf& as = switches[i];
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R = Cin = Cint = Cout = Tdel = 0.0;
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SwitchType type;
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350+
if (i == 0) {
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switch_name = "short";
352+
type = SwitchType::SHORT;
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R = 0.0;
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} else if (i == 1) {
355+
switch_name = "generic";
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type = SwitchType::MUX;
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R = 0.0;
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} else {
359+
auto entry = pip_timing_models_list[i - 2];
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auto model = timing_data[entry.second];
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std::stringstream name;
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std::string mux_type_string = entry.first ? "mux_" : "passGate_";
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name << mux_type_string;
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365+
R = get_corner_value(model.getOutputResistance(), "slow", "min");
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name << "R" << std::scientific << R;
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Cin = get_corner_value(model.getInputCapacitance(), "slow", "min");
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name << "Cin" << std::scientific << Cin;
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Cout = get_corner_value(model.getOutputCapacitance(), "slow", "min");
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name << "Cout" << std::scientific << Cout;
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374+
if (entry.first) {
375+
Cint = get_corner_value(model.getInternalCapacitance(), "slow", "min");
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name << "Cinternal" << std::scientific << Cint;
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}
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379+
Tdel = get_corner_value(model.getInternalDelay(), "slow", "min");
380+
name << "Tdel" << std::scientific << Tdel;
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382+
switch_name = name.str();
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type = entry.first ? SwitchType::MUX : SwitchType::PASS_GATE;
384+
}
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/* Should never happen */
387+
if (switch_name == std::string(VPR_DELAYLESS_SWITCH_NAME)) {
388+
archfpga_throw(arch_file_, __LINE__,
389+
"Switch name '%s' is a reserved name for VPR internal usage!", switch_name.c_str());
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}
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392+
as.name = vtr::strdup(switch_name.c_str());
393+
as.set_type(type);
394+
as.mux_trans_size = as.type() == SwitchType::MUX ? 1 : 0;
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396+
as.R = R;
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as.Cin = Cin;
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as.Cout = Cout;
399+
as.Cinternal = Cint;
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as.set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, Tdel);
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402+
if (as.type() == SwitchType::SHORT || as.type() == SwitchType::PASS_GATE) {
403+
as.buf_size_type = BufferSize::ABSOLUTE;
404+
as.buf_size = 0;
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as.power_buffer_type = POWER_BUFFER_TYPE_ABSOLUTE_SIZE;
406+
as.power_buffer_size = 0.;
407+
} else {
408+
as.buf_size_type = BufferSize::AUTO;
409+
as.buf_size = 0.;
410+
as.power_buffer_type = POWER_BUFFER_TYPE_AUTO;
411+
}
412+
}
413+
}
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415+
void process_segments() {
416+
// Segment names will be taken from wires connected to pips
417+
// They are good representation for nodes
418+
std::set<uint32_t> wire_names;
419+
for (auto tile_type : ar_.getTileTypeList()) {
420+
auto wires = tile_type.getWires();
421+
for (auto pip : tile_type.getPips()) {
422+
wire_names.insert(wires[pip.getWire0()]);
423+
wire_names.insert(wires[pip.getWire1()]);
424+
}
425+
}
426+
int numSeg = wire_names.size();
427+
arch_->Segments.resize(numSeg);
428+
uint32_t index = 0;
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for (auto i : wire_names) {
430+
// Use default values as we will populate rr_graph with correct values
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// This segments are just declaration of future use
432+
arch_->Segments[index].name = str(i);
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arch_->Segments[index].length = 1;
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arch_->Segments[index].frequency = 1;
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arch_->Segments[index].Rmetal = 0;
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arch_->Segments[index].Cmetal = 0;
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arch_->Segments[index].parallel_axis = BOTH_AXIS;
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arch_->Segments[index].directionality = BI_DIRECTIONAL;
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arch_->Segments[index].arch_wire_switch = 1;
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arch_->Segments[index].arch_opin_switch = 1;
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arch_->Segments[index].cb.resize(1);
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arch_->Segments[index].cb[0] = true;
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arch_->Segments[index].sb.resize(2);
444+
arch_->Segments[index].sb[0] = true;
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arch_->Segments[index].sb[1] = true;
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++index;
447+
}
448+
}
166449
};
167450

168451
void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile,

‎vpr/test/test_interchange_device.cpp

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,4 +41,30 @@ TEST_CASE("read_interchange_models", "[vpr]") {
4141
REQUIRE(lib_models.size() == 0);
4242
}
4343

44+
TEST_CASE("read_interchange_layout", "[vpr]") {
45+
t_arch arch;
46+
std::vector<t_physical_tile_type> physical_tile_types;
47+
std::vector<t_logical_block_type> logical_block_types;
48+
49+
FPGAInterchangeReadArch(kArchFile, /*timing_enabled=*/true, &arch, physical_tile_types, logical_block_types);
50+
51+
auto& gd = arch.grid_layouts[0];
52+
REQUIRE(gd.grid_type == GridDefType::FIXED);
53+
REQUIRE(gd.height == 10);
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REQUIRE(gd.width == 10);
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std::unordered_map<std::string, bool> tile_types({{"NULL", false}, {"PWR", false}, {"IOB", false}, {"CLB", false}});
57+
for (auto& loc : gd.loc_defs) {
58+
auto ret = tile_types.find(loc.block_type);
59+
REQUIRE(ret != tile_types.end());
60+
REQUIRE(loc.priority == 1);
61+
62+
ret->second = true;
63+
}
64+
65+
for (auto type : tile_types) {
66+
CHECK(type.second);
67+
}
68+
}
69+
4470
} // namespace

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