File tree 4 files changed +10
-10
lines changed
vtr_flow/tasks/regression_tests
strong_place_delay_calc_method/config
strong_custom_pin_locs/config
4 files changed +10
-10
lines changed Original file line number Diff line number Diff line change 11arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.82 vpr 63.97 MiB -1 -1 0.58 25532 5 0.16 -1 -1 36972 -1 -1 12 10 0 0 success b93114b release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-05-16T13:37:54 gh-actions-runner-vtr-auto-spawned30 /root/ vtr-verilog-to-routing /vtr-verilog-to-routing 65508 10 2 181 183 1 40 24 6 6 36 clb auto 25.5 MiB 0.04 174 92 23 64 5 64.0 MiB 0.01 0.00 2.07517 -86.4376 -2.07517 2.07517 0.05 0.000355588 0.000315311 0.00287009 0.00268552 8 234 44 646728 646728 33486.6 930.184 0.21 0.0643387 0.0544077 1588 8314 -1 240 19 270 565 23832 7408 2.63212 2.63212 -118.257 -2.63212 0 0 42482.2 1180.06 0.01 0.03 0.01 -1 -1 0.01 0.0164962 0.0145092
2+ k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 3.26 vpr 60.91 MiB -1 -1 0.72 22552 5 0.45 -1 -1 33444 -1 -1 12 10 0 0 success v8.0.0-10480-g679618a2e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-06-23T21:50:39 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/ vtr/vtr-verilog-to-routing/vtr_flow/tasks 62376 10 2 181 183 1 40 24 6 6 36 clb auto 22.2 MiB 0.04 174 92 23 64 5 60.9 MiB 0.01 0.00 2.07517 -86.4376 -2.07517 2.07517 0.04 0.000492958 0.000453322 0.00292737 0.00275391 12 210 19 646728 646728 46454.1 1290.39 0.25 0.104303 0.0865769 1696 12788 -1 190 14 229 450 16294 3769 2.31307 2.31307 -105.081 -2.31307 0 0 57919.4 1608.87 0.01 0.03 0.01 -1 -1 0.01 0.0152419 0.0132254
Original file line number Diff line number Diff line change 11arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 39.81 vpr 978.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 106a52a release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-03-01T18:56:15 gh-actions-runner-vtr-auto-spawned12 /root/ vtr-verilog-to-routing /vtr-verilog-to-routing 1001932 10 10 168 178 1 62 30 11 8 88 io auto 954 .7 MiB 0.59 345 766 84 629 53 978 .4 MiB 0.05 0.00 6.42093 -69.165 -6.42093 6.42093 3.07 0.000437885 0.00039127 0.0125651 0.0115806 20 749 20 0 0 100248. 1139.18 1.73 0.19564 0.171991 11180 23751 -1 759 16 363 1367 129159 52560 7.05752 7.05752 -76.511 -7.05752 0 0 125464. 1425.72 0.03 0.08 0.08 -1 -1 0.03 0.0329119 0.0303443
3- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 40.02 vpr 978.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 106a52a release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-03-01T18:56:15 gh-actions-runner-vtr-auto-spawned12 /root/ vtr-verilog-to-routing /vtr-verilog-to-routing 1001908 10 10 168 178 1 62 30 11 8 88 io auto 954 .8 MiB 0.62 344 720 82 581 57 978.4 MiB 0.05 0.00 6.39032 -69.1435 -6.39032 6.39032 3.05 0.000477436 0.000414516 0.0134354 0.0123555 18 826 22 0 0 88979.3 1011.13 1.84 0.21881 0.191881 11100 22242 -1 787 17 455 1856 167337 66315 7.03645 7.03645 -77.7495 -7.03645 0 0 114778. 1304.29 0.03 0.08 0.08 -1 -1 0.03 0.0333434 0.0307725
4- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 40.20 vpr 978.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 106a52a release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-03-01T18:56:15 gh-actions-runner-vtr-auto-spawned12 /root/ vtr-verilog-to-routing /vtr-verilog-to-routing 1001904 10 10 168 178 1 62 30 11 8 88 io auto 954.7 MiB 0.62 334 766 75 633 58 978.4 MiB 0.05 0.00 6.24004 -68.8638 -6.24004 6.24004 4.21 0.00043712 0.00039058 0.0135251 0.0124714 20 746 22 0 0 100248. 1139.18 0.58 0.10259 0.0909598 11180 23751 -1 649 15 376 1644 145960 58750 6.75777 6.75777 -74.5795 -6.75777 0 0 125464. 1425.72 0.04 0.08 0.08 -1 -1 0.04 0.0325761 0.0301424
5- stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.96 vpr 978.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success 106a52a release IPO VTR_ASSERT_LEVEL=3 GNU 9.5 .0 on Linux-5.10.35-v8 x86_64 2024-03-01T18:56:15 gh-actions-runner-vtr-auto-spawned12 /root/ vtr-verilog-to-routing /vtr-verilog-to-routing 1002092 10 10 168 178 1 62 30 11 8 88 io auto 954.8 MiB 0.62 339 720 76 599 45 978.6 MiB 0.05 0.00 6.3798 -68.6604 -6.3798 6.3798 4.27 0.000432929 0.000377889 0.0149805 0.0140656 18 805 24 0 0 88979.3 1011.13 2.25 0.280633 0.247426 11100 22242 -1 659 19 387 1549 135401 55869 6.92851 6.92851 -76.1613 -6.92851 0 0 114778. 1304.29 0.03 0.08 0.07 -1 -1 0.03 0.0337395 0.0309553
2+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 31.68 vpr 976.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-10480-g679618a2e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-06-23T21:50:39 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/ vtr/vtr-verilog-to-routing/vtr_flow/tasks 999828 10 10 168 178 1 62 30 11 8 88 io auto 952 .7 MiB 0.49 368 766 91 620 55 976 .4 MiB 0.07 0.00 6.32355 -69.2597 -6.32355 6.32355 3.03 0.000606959 0.000542424 0.0138306 0.0128873 28 702 21 0 0 134428. 1527.59 0.57 0.101778 0.0894085 11590 29630 -1 622 11 230 891 89731 31995 6.89935 6.89935 -73.8866 -6.89935 0 0 173354. 1969.93 0.03 0.06 0.10 -1 -1 0.03 0.0214102 0.0193672
3+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 32.09 vpr 976.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-10480-g679618a2e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-06-23T21:50:39 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/ vtr/vtr-verilog-to-routing/vtr_flow/tasks 999936 10 10 168 178 1 62 30 11 8 88 io auto 952 .8 MiB 0.49 344 720 82 581 57 976.5 MiB 0.07 0.00 6.39032 -69.1435 -6.39032 6.39032 3.04 0.000600169 0.000551234 0.0130613 0.0122073 18 839 22 0 0 88979.3 1011.13 0.65 0.101009 0.0885949 11100 22242 -1 762 18 447 1915 168871 66281 7.03645 7.03645 -77.8983 -7.03645 0 0 114778. 1304.29 0.02 0.08 0.09 -1 -1 0.02 0.0279206 0.0247821
4+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.28 vpr 976.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-10480-g679618a2e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-06-23T21:50:39 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/ vtr/vtr-verilog-to-routing/vtr_flow/tasks 999896 10 10 168 178 1 62 30 11 8 88 io auto 952.8 MiB 0.49 334 766 75 633 58 976.5 MiB 0.10 0.00 6.24004 -68.8638 -6.24004 6.24004 4.07 0.000634706 0.000586765 0.0149754 0.0140212 18 899 39 0 0 88979.3 1011.13 0.73 0.110608 0.0954776 11100 22242 -1 696 22 510 2363 198597 78898 6.62875 6.62875 -75.2001 -6.62875 0 0 114778. 1304.29 0.02 0.10 0.09 -1 -1 0.02 0.0320727 0.028307
5+ stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 34.15 vpr 976.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-10480-g679618a2e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213-generic x86_64 2024-06-23T21:50:39 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/ vtr/vtr-verilog-to-routing/vtr_flow/tasks 999816 10 10 168 178 1 62 30 11 8 88 io auto 952.7 MiB 0.50 339 720 76 599 45 976.4 MiB 0.08 0.00 6.3798 -68.6604 -6.3798 6.3798 4.15 0.000660135 0.000609847 0.0138725 0.0129932 18 811 22 0 0 88979.3 1011.13 0.62 0.0967468 0.0834932 11100 22242 -1 677 19 362 1443 129672 53439 6.93449 6.93449 -74.8141 -6.93449 0 0 114778. 1304.29 0.02 0.08 0.09 -1 -1 0.02 0.0289955 0.0256269
Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 5.54 vpr 62.11 MiB 0.09 9428 -1 -1 3 0.28 -1 -1 36388 -1 -1 65 99 1 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5 .0 on Linux-4.15.0-167 -generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor /vtr-verilog-to-routing 63596 99 130 363 493 1 251 295 12 12 144 clb auto 24.0 MiB 0.31 686 62.1 MiB 0.45 0.00 2.09536 -200 -2.09536 2.09536 0.39 0.000659078 0.000579598 0.0648306 0.0586616 36 1781 16 5.66058e+06 4.05111e+06 314518. 2184.15 2.05 0.327517 0.299975 1452 8 533 700 58546 20432 2.70931 2.70931 -237.037 -2.70931 0 0 390367. 2710.88 0.12 0. 10 0.0222878 0.0211727
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 4.11 vpr 64.18 MiB 0.11 9384 -1 -1 3 0.25 -1 -1 34556 -1 -1 65 99 1 0 success v8.0.0-10480-g679618a2e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4 .0 on Linux-4.15.0-213 -generic x86_64 2024-06-23T21:50:39 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr /vtr-verilog-to-routing/vtr_flow/tasks 65720 99 130 363 493 1 251 295 12 12 144 clb auto 25.7 MiB 0.12 622 69946 24703 33944 11299 64.2 MiB 0.26 0.00 2.16091 -205.436 -2.16091 2.16091 0.29 0.0012912 0.0012237 0.0961186 0.0910662 48 1444 10 5.66058e+06 4.05111e+06 405754. 2817.73 1.54 0.404478 0.371498 13382 80270 -1 1262 8 582 753 44166 14431 2.70001 2.70001 -235.841 -2.70001 0 0 516884. 3589.47 0.10 0.05 0.08 -1 -1 0. 10 0.0277344 0.0257451
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