replace t_clb_to_clb_directs* with std::vector<t_clb_to_clb_directs>&

Author: soheilshahrouz

vpr/src/route/rr_graph.cpp

@@ -155,7 +155,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder,
                                  const t_chan_details& chan_details_y,
                                  const DeviceGrid& grid,
                                  const std::vector<t_direct_inf>& directs,
-                                 const t_clb_to_clb_directs* clb_to_clb_directs,
+                                 const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs,
                                  const int num_seg_types);
 
 static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder,
@@ -175,7 +175,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder,
                                   bool* Fc_clipped,
                                   const t_unified_to_parallel_seg_index& seg_index_map,
                                   const std::vector<t_direct_inf>& directs,
-                                  const t_clb_to_clb_directs* clb_to_clb_directs,
+                                  const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs,
                                   const int num_seg_types,
                                   int& edge_count);
 
@@ -189,7 +189,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder,
                                        RRNodeId from_rr_node,
                                        t_rr_edge_info_set& rr_edges_to_create,
                                        const std::vector<t_direct_inf>& directs,
-                                       const t_clb_to_clb_directs* clb_to_clb_directs);
+                                       const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs);
 
 static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder& rr_graph_builder,
                                                                   t_rr_graph_storage& L_rr_node,
@@ -218,7 +218,7 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
                                                                   const enum e_directionality directionality,
                                                                   bool* Fc_clipped,
                                                                   const std::vector<t_direct_inf>& directs,
-                                                                  const t_clb_to_clb_directs* clb_to_clb_directs,
+                                                                  const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs,
                                                                   bool is_global_graph,
                                                                   const enum e_clock_modeling clock_modeling,
                                                                   bool is_flat,
@@ -596,7 +596,8 @@ static void rr_graph_externals(const std::vector<t_segment_inf>& segment_inf,
                                int wire_to_rr_ipin_switch,
                                enum e_base_cost_type base_cost_type);
 
-static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector<t_direct_inf>& directs, const int delayless_switch);
+static std::vector<t_clb_to_clb_directs> alloc_and_load_clb_to_clb_directs(const std::vector<t_direct_inf>& directs,
+                                                                           int delayless_switch);
 
 static std::vector<t_seg_details> alloc_and_load_global_route_seg_details(int global_route_switch);
 
@@ -1106,10 +1107,7 @@ static void build_rr_graph(const t_graph_type graph_type,
     auto& device_ctx = g_vpr_ctx.mutable_device();
     const auto& rr_graph = device_ctx.rr_graph;
 
-    t_clb_to_clb_directs* clb_to_clb_directs = nullptr;
-    if (!directs.empty()) {
-        clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch);
-    }
+    std::vector<t_clb_to_clb_directs> clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch);
 
     /* START SEG_DETAILS */
     size_t num_segments = segment_inf.size();
@@ -1564,11 +1562,6 @@ static void build_rr_graph(const t_graph_type graph_type,
 
     track_to_pin_lookup_x.clear();
     track_to_pin_lookup_y.clear();
-
-    if (clb_to_clb_directs != nullptr) {
-        delete[] clb_to_clb_directs;
-    }
-
     // We are done with building the RR Graph. Thus, we can clear the storages only used
     // to build the RR Graph
     device_ctx.rr_graph_builder.clear_temp_storage();
@@ -2150,11 +2143,12 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
                                                                   const enum e_directionality directionality,
                                                                   bool* Fc_clipped,
                                                                   const std::vector<t_direct_inf>& directs,
-                                                                  const t_clb_to_clb_directs* clb_to_clb_directs,
+                                                                  const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs,
                                                                   bool is_global_graph,
                                                                   const enum e_clock_modeling clock_modeling,
                                                                   bool /*is_flat*/,
                                                                   const int route_verbosity) {
+    VTR_ASSERT(directs.size() == clb_to_clb_directs.size());
     //We take special care when creating RR graph edges (there are typically many more
     //edges than nodes in an RR graph).
     //
@@ -2734,7 +2728,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder,
                                  const t_chan_details& chan_details_y,
                                  const DeviceGrid& grid,
                                  const std::vector<t_direct_inf>& directs,
-                                 const t_clb_to_clb_directs* clb_to_clb_directs,
+                                 const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs,
                                  const int num_seg_types) {
     //Don't connect pins which are not adjacent to channels around the perimeter
     if ((i == 0 && side != RIGHT)
@@ -4234,7 +4228,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder,
                                   bool* Fc_clipped,
                                   const t_unified_to_parallel_seg_index& seg_index_map,
                                   const std::vector<t_direct_inf>& directs,
-                                  const t_clb_to_clb_directs* clb_to_clb_directs,
+                                  const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs,
                                   const int num_seg_types,
                                   int& rr_edge_count) {
     /*
@@ -4343,15 +4337,12 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder,
  * This data structure supplements the the info in the "directs" data structure
  * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one
  */
-static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector<t_direct_inf>& directs, int delayless_switch) {
-    t_clb_to_clb_directs* clb_to_clb_directs;
-    t_physical_tile_type_ptr physical_tile = nullptr;
-    t_physical_tile_port tile_port;
-
-    auto& device_ctx = g_vpr_ctx.device();
+static std::vector<t_clb_to_clb_directs> alloc_and_load_clb_to_clb_directs(const std::vector<t_direct_inf>& directs,
+                                                                           int delayless_switch) {
+    const auto& device_ctx = g_vpr_ctx.device();
 
-    const int num_directs = directs.size();
-    clb_to_clb_directs = new t_clb_to_clb_directs[num_directs];
+    const int num_directs = (int)directs.size();
+    std::vector<t_clb_to_clb_directs> clb_to_clb_directs(num_directs);
 
     for (int i = 0; i < num_directs; i++) {
         //clb_to_clb_directs[i].from_clb_type;
@@ -4367,20 +4358,15 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector
         auto [start_pin_index, end_pin_index, tile_name, port_name] = parse_direct_pin_name(directs[i].from_pin, directs[i].line);
 
         // Figure out which type, port, and pin is used
-        for (const t_physical_tile_type& type : device_ctx.physical_tile_types) {
-            if (tile_name == type.name) {
-                physical_tile = &type;
-                break;
-            }
-        }
+        t_physical_tile_type_ptr physical_tile = find_tile_type_by_name(tile_name, device_ctx.physical_tile_types);
 
         if (physical_tile == nullptr) {
             VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name.c_str());
         }
 
         clb_to_clb_directs[i].from_clb_type = physical_tile;
 
-        tile_port = find_tile_port_by_name(physical_tile, port_name);
+        t_physical_tile_port tile_port = find_tile_port_by_name(physical_tile, port_name);
 
         if (start_pin_index == OPEN) {
             VTR_ASSERT(start_pin_index == end_pin_index);
@@ -4456,7 +4442,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder,
                                        RRNodeId from_rr_node,
                                        t_rr_edge_info_set& rr_edges_to_create,
                                        const std::vector<t_direct_inf>& directs,
-                                       const t_clb_to_clb_directs* clb_to_clb_directs) {
+                                       const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs) {
     auto& device_ctx = g_vpr_ctx.device();
 
     t_physical_tile_type_ptr curr_type = device_ctx.grid.get_physical_type({x, y, layer});
@@ -4585,7 +4571,6 @@ static std::vector<bool> alloc_and_load_perturb_opins(const t_physical_tile_type
                                                       const std::vector<t_segment_inf>& segment_inf) {
     int i, Fc_max, iclass, num_wire_types;
     int num, max_primes, factor, num_factors;
-    int* prime_factors;
     float step_size = 0;
     float n = 0;
     float threshold = 0.07;
@@ -4629,10 +4614,7 @@ static std::vector<bool> alloc_and_load_perturb_opins(const t_physical_tile_type
     max_primes = (int)floor(log((float)num_wire_types) / log(2.0));
     max_primes = std::max(max_primes, 1); //Minimum of 1 to ensure we allocate space for at least one prime_factor
 
-    prime_factors = new int[max_primes];
-    for (i = 0; i < max_primes; i++) {
-        prime_factors[i] = 0;
-    }
+    std::vector<int>prime_factors(max_primes, 0);
 
     /* Find the prime factors of num_wire_types */
     num = num_wire_types;
@@ -4671,7 +4653,6 @@ static std::vector<bool> alloc_and_load_perturb_opins(const t_physical_tile_type
             perturb_opins[0] = false;
         }
     }
-    delete[] prime_factors;
 
     return perturb_opins;
 }