Merge pull request #2175 from verilog-to-routing/centroid_placement

Centroid placement

Author: vaughnbetz

vpr/src/pack/re_cluster_util.cpp

@@ -82,7 +82,7 @@ void commit_mol_move(const ClusterBlockId& old_clb,
         g_vpr_ctx.mutable_placement().block_locs.resize(g_vpr_ctx.placement().block_locs.size() + 1);
         get_imacro_from_iblk(&imacro, old_clb, g_vpr_ctx.placement().pl_macros);
         set_imacro_for_iblk(&imacro, new_clb);
-        place_one_block(new_clb, device_ctx.pad_loc_type, NULL);
+        place_one_block(new_clb, device_ctx.pad_loc_type, NULL, NULL);
     }
 }
 

vpr/src/place/initial_placement.cpp

@@ -3,6 +3,24 @@
 
 #include "vpr_types.h"
 
+/**
+ * @brief Used to assign each block a score for how difficult it is to place. 
+ * The higher numbers indicate a block is expected to be more difficult to place.
+ * Hence, initial placement tries to place blocks with higher scores earlier.
+ */
+struct t_block_score {
+    int macro_size = 0; //How many members does the macro have, if the block is part of one - this value is zero if the block is not in a macro
+
+    //The number of tiles NOT covered by the block's floorplan constraints.
+    double tiles_outside_of_floorplan_constraints = 0;
+
+    //The number of initial placement iterations that the block was unplaced.
+    int failed_to_place_in_prev_attempts;
+
+    //The number of placed block during initial placement that are connected to the this block.
+    int number_of_placed_connections = 0;
+};
+
 /**
  * @brief keeps track of available empty locations of a specific block type during initial placement.
  * Used to densly place macros that failed to be placed in the first initial placement iteration (random placement)
@@ -39,5 +57,5 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, const char* constraints
  * 
  * @return true if the block gets placed, false if not.
  */
-bool place_one_block(const ClusterBlockId& blk_id, enum e_pad_loc_type pad_loc_type, std::vector<t_grid_empty_locs_block_type>* blk_types_empty_locs_in_grid);
+bool place_one_block(const ClusterBlockId& blk_id, enum e_pad_loc_type pad_loc_type, std::vector<t_grid_empty_locs_block_type>* blk_types_empty_locs_in_grid, vtr::vector<ClusterBlockId, t_block_score>* block_scores);
 #endif

vpr/src/place/initial_placement.h

@@ -527,6 +527,7 @@ void try_place(const t_placer_opts& placer_opts,
     if (placer_opts.enable_analytic_placer) {
         AnalyticPlacer{}.ap_place();
     }
+
 #endif /* ENABLE_ANALYTIC_PLACE */
 
     // Update physical pin values
@@ -719,9 +720,8 @@ void try_place(const t_placer_opts& placer_opts,
                             device_ctx.grid.height() - 1);
     place_move_ctx.first_rlim = first_rlim;
 
-    /* Set the temperature high so essentially all swaps will be accepted   */
-    /* when trying to determine the starting temp for placement inner loop. */
-    first_t = HUGE_POSITIVE_FLOAT;
+    /* Set the temperature low to ensure that initial placement quality will be preserved */
+    first_t = EPSILON;
 
     t_annealing_state state(annealing_sched, first_t, first_rlim,
                             first_move_lim, first_crit_exponent);
@@ -1252,9 +1252,13 @@ static float starting_t(const t_annealing_state* state, t_placer_costs* costs, t
     VTR_LOG("std_dev: %g, average cost: %g, starting temp: %g\n", std_dev, av, 20. * std_dev);
 #endif
 
-    /* Set the initial temperature to 20 times the standard of deviation */
+    /* Set the initial temperature to the standard of deviation divided by 64 */
     /* so that the initial temperature adjusts according to the circuit */
-    return (20. * std_dev);
+    /* and also keep the initial placement qaulity (not destroying it completely) */
+    /* and fine-tune the initial placement with the anneal*/
+    float init_temp = (std_dev / 64);
+
+    return init_temp;
 }
 
 static void update_move_nets(int num_nets_affected) {

vpr/src/place/place.cpp

@@ -425,7 +425,7 @@ int get_part_reg_size(PartitionRegion& pr, t_logical_block_type_ptr block_type,
     return num_tiles;
 }
 
-int get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles) {
+double get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
     int num_pr_tiles = get_part_reg_size(pr, block_type, grid_tiles);
@@ -441,5 +441,5 @@ int get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_bl
 
     int total_type_tiles = grid_tiles.total_type_tiles(block_type);
 
-    return total_type_tiles - num_pr_tiles;
+    return (double)(total_type_tiles - num_pr_tiles) / total_type_tiles;
 }

vpr/src/place/place_constraints.cpp

@@ -130,6 +130,6 @@ int get_part_reg_size(PartitionRegion& pr, t_logical_block_type_ptr block_type,
  * The resulting number is the number of tiles outside the block's floorplan region, meaning the higher
  * it is, the more difficult the block is to place.
  */
-int get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles);
+double get_floorplan_score(ClusterBlockId blk_id, PartitionRegion& pr, t_logical_block_type_ptr block_type, GridTileLookup& grid_tiles);
 
 #endif /* VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ */

vpr/src/place/place_constraints.h

@@ -462,6 +462,8 @@ void set_block_location(ClusterBlockId blk_id, const t_pl_loc& location) {
     //Mark the grid location and usage of the block
     place_ctx.grid_blocks[location.x][location.y].blocks[location.sub_tile] = blk_id;
     place_ctx.grid_blocks[location.x][location.y].usage++;
+
+    place_sync_external_block_connections(blk_id);
 }
 
 bool macro_can_be_placed(t_pl_macro pl_macro, t_pl_loc head_pos, bool check_all_legality) {

vpr/src/place/place_util.cpp

@@ -1,9 +1,9 @@
-arch	circuit	script_params	vtr_flow_elapsed_time	error	odin_synth_time	max_odin_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_time	placed_wirelength_est	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k6_N10_mem32K_40nm.xml	ch_intrinsics.v	common	1.94		0.05	9260	3	0.18	-1	-1	36124	-1	-1	70	99	1	0	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	36124	99	130	363	493	1	255	300	12	12	144	clb	auto	0.05	-1	0.26	0.00	2.05524	-206.163	-2.05524	2.05524	0.18	0.000403663	0.000345944	0.0677313	0.0579949	42	1187	22	5.66058e+06	4.32058e+06	330626.	2296.01	0.41	0.138068	0.121079	1095	29	798	1106	131444	46872	2.35944	2.35944	-229.387	-2.35944	0	0	415849.	2887.84	0.08	0.05	0.0261994	0.0237543	
-k6_N10_mem32K_40nm.xml	ch_intrinsics.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	1.91		0.04	9224	3	0.18	-1	-1	36104	-1	-1	70	99	1	0	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	35484	99	130	363	493	1	255	300	12	12	144	clb	auto	0.05	-1	0.25	0.00	2.05524	-206.163	-2.05524	2.05524	0.18	0.000416229	0.000359616	0.0671649	0.0575863	42	1187	22	5.66058e+06	4.32058e+06	330626.	2296.01	0.42	0.137699	0.120965	1095	29	798	1106	131444	46872	2.35944	2.35944	-229.387	-2.35944	0	0	415849.	2887.84	0.07	0.05	0.0253714	0.0229951	
-k6_N10_mem32K_40nm.xml	diffeq1.v	common	8.59		0.04	9216	15	0.27	-1	-1	34532	-1	-1	52	162	0	5	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	46868	162	96	999	932	1	707	315	16	16	256	mult_36	auto	0.15	-1	0.50	0.01	19.9852	-1704.83	-19.9852	19.9852	0.37	0.00131942	0.00118473	0.191764	0.168834	48	11166	39	1.21132e+07	4.78249e+06	721839.	2819.68	5.59	0.843816	0.759518	9306	20	3659	7667	2417287	591248	21.7161	21.7161	-1952.84	-21.7161	0	0	926152.	3617.78	0.16	0.35	0.0731877	0.0676767	
-k6_N10_mem32K_40nm.xml	diffeq1.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	8.84		0.03	9184	15	0.35	-1	-1	34736	-1	-1	52	162	0	5	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	51052	162	96	999	932	1	707	315	16	16	256	mult_36	auto	0.16	-1	0.50	0.01	19.9852	-1704.83	-19.9852	19.9852	0.39	0.00131301	0.00117586	0.193278	0.170331	48	11166	39	1.21132e+07	4.78249e+06	721839.	2819.68	5.63	0.854207	0.769296	9306	20	3659	7667	2417287	591248	21.7161	21.7161	-1952.84	-21.7161	0	0	926152.	3617.78	0.17	0.35	0.0734365	0.0678236	
-k6_N10_mem32K_40nm.xml	single_wire.v	common	0.31		0.01	5672	1	0.00	-1	-1	29364	-1	-1	0	1	0	0	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	24896	1	1	1	2	0	1	2	3	3	9	-1	auto	0.00	-1	0.00	0.00	0.205011	-0.205011	-0.205011	nan	0.00	9.505e-06	5.841e-06	5.4583e-05	3.2588e-05	2	1	1	53894	0	1165.58	129.509	0.00	0.000150654	8.7624e-05	1	1	1	1	20	17	0.212085	nan	-0.212085	-0.212085	0	0	1165.58	129.509	0.00	0.00	8.33e-05	5.3203e-05	
-k6_N10_mem32K_40nm.xml	single_wire.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.32		0.02	5592	1	0.00	-1	-1	29388	-1	-1	0	1	0	0	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	24748	1	1	1	2	0	1	2	3	3	9	-1	auto	0.00	-1	0.00	0.00	0.205011	-0.205011	-0.205011	nan	0.00	9.273e-06	5.723e-06	5.3969e-05	3.2658e-05	2	1	1	53894	0	1165.58	129.509	0.00	0.000146431	8.851e-05	1	1	1	1	20	17	0.212085	nan	-0.212085	-0.212085	0	0	1165.58	129.509	0.00	0.00	7.0465e-05	4.2406e-05	
-k6_N10_mem32K_40nm.xml	single_ff.v	common	0.34		0.03	5568	1	0.00	-1	-1	29344	-1	-1	1	2	0	0	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	24852	2	1	3	4	1	3	4	3	3	9	-1	auto	0.00	-1	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.00	1.3013e-05	8.774e-06	8.1061e-05	5.4348e-05	2	4	2	53894	53894	1165.58	129.509	0.00	0.000233794	0.000154777	4	2	3	3	73	45	0.576831	0.576831	-1.12264	-0.576831	0	0	1165.58	129.509	0.00	0.00	0.000133632	8.6366e-05	
-k6_N10_mem32K_40nm.xml	single_ff.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.76		0.02	5748	1	0.01	-1	-1	29216	-1	-1	1	2	0	0	success	v8.0.0-4627-ga24fa2acd	release IPO VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-60-generic x86_64	2021-10-06T11:31:46	betzgrp-wintermute.eecg.utoronto.ca	/home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks	24964	2	1	3	4	1	3	4	3	3	9	-1	auto	0.00	-1	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.00	1.4127e-05	9.491e-06	9.3861e-05	6.6395e-05	2	4	2	53894	53894	1165.58	129.509	0.00	0.000359535	0.000226429	4	2	3	3	73	45	0.576831	0.576831	-1.12264	-0.576831	0	0	1165.58	129.509	0.00	0.00	0.000134396	8.744e-05	
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+k6_N10_mem32K_40nm.xml	ch_intrinsics.v	common	2.13	vpr	61.64 MiB		0.04	9172	-1	-1	3	0.20	-1	-1	36164	-1	-1	70	99	1	0	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	63116	99	130	363	493	1	255	300	12	12	144	clb	auto	22.9 MiB	0.07	651	61.6 MiB	0.09	0.00	2.12937	-209.611	-2.12937	2.12937	0.23	0.000354388	0.00031469	0.0225691	0.0202115	38	1263	13	5.66058e+06	4.32058e+06	306247.	2126.71	0.50	0.109377	0.100354	1135	11	713	1002	85314	26625	2.59213	2.59213	-228.948	-2.59213	0	0	388532.	2698.14	0.09	0.03	0.0141691	0.0133644	
+k6_N10_mem32K_40nm.xml	ch_intrinsics.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	2.11	vpr	61.80 MiB		0.04	9364	-1	-1	3	0.19	-1	-1	36164	-1	-1	70	99	1	0	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	63284	99	130	363	493	1	255	300	12	12	144	clb	auto	23.1 MiB	0.05	651	61.8 MiB	0.09	0.00	2.12937	-209.611	-2.12937	2.12937	0.23	0.000360754	0.000320981	0.0230926	0.0207354	38	1263	13	5.66058e+06	4.32058e+06	306247.	2126.71	0.52	0.111958	0.102971	1135	11	713	1002	85314	26625	2.59213	2.59213	-228.948	-2.59213	0	0	388532.	2698.14	0.09	0.03	0.0140572	0.0132597	
+k6_N10_mem32K_40nm.xml	diffeq1.v	common	7.08	vpr	65.52 MiB		0.04	9236	-1	-1	15	0.31	-1	-1	34596	-1	-1	52	162	0	5	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	67096	162	96	999	932	1	707	315	16	16	256	mult_36	auto	27.6 MiB	0.16	5727	65.5 MiB	0.37	0.01	20.0262	-1714.67	-20.0262	20.0262	0.48	0.00149324	0.0013599	0.144117	0.133364	44	12591	46	1.21132e+07	4.78249e+06	665287.	2598.78	3.74	0.679764	0.636856	9894	24	4260	8861	2354606	554199	21.727	21.727	-1882.12	-21.727	0	0	864808.	3378.16	0.20	0.39	0.0964146	0.0914499	
+k6_N10_mem32K_40nm.xml	diffeq1.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	7.60	vpr	65.39 MiB		0.04	9160	-1	-1	15	0.31	-1	-1	34768	-1	-1	52	162	0	5	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	66956	162	96	999	932	1	707	315	16	16	256	mult_36	auto	27.5 MiB	0.16	5727	65.4 MiB	0.36	0.01	20.0262	-1714.67	-20.0262	20.0262	0.51	0.00150881	0.00139739	0.142806	0.13209	44	12591	46	1.21132e+07	4.78249e+06	665287.	2598.78	4.07	0.671994	0.629839	9894	24	4260	8861	2354606	554199	21.727	21.727	-1882.12	-21.727	0	0	864809.	3378.16	0.21	0.49	0.113204	0.107601	
+k6_N10_mem32K_40nm.xml	single_wire.v	common	0.42	vpr	58.62 MiB		0.03	5732	-1	-1	1	0.01	-1	-1	29292	-1	-1	0	1	0	0	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	60024	1	1	1	2	0	1	2	3	3	9	-1	auto	19.4 MiB	0.00	2	58.6 MiB	0.00	0.00	0.205011	-0.205011	-0.205011	nan	0.00	4.468e-06	2.04e-06	2.9487e-05	1.562e-05	2	1	1	53894	0	1165.58	129.509	0.00	8.8637e-05	5.4317e-05	1	1	1	1	17	8	0.211201	nan	-0.211201	-0.211201	0	0	1165.58	129.509	0.00	0.00	4.2405e-05	2.7206e-05	
+k6_N10_mem32K_40nm.xml	single_wire.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.41	vpr	58.52 MiB		0.01	5808	-1	-1	1	0.01	-1	-1	29288	-1	-1	0	1	0	0	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	59928	1	1	1	2	0	1	2	3	3	9	-1	auto	19.3 MiB	0.01	2	58.5 MiB	0.00	0.00	0.205011	-0.205011	-0.205011	nan	0.00	4.452e-06	2.13e-06	2.923e-05	1.5809e-05	2	1	1	53894	0	1165.58	129.509	0.00	8.1703e-05	4.843e-05	1	1	1	1	17	8	0.211201	nan	-0.211201	-0.211201	0	0	1165.58	129.509	0.00	0.00	4.2153e-05	2.6712e-05	
+k6_N10_mem32K_40nm.xml	single_ff.v	common	0.42	vpr	58.31 MiB		0.01	5732	-1	-1	1	0.00	-1	-1	29188	-1	-1	1	2	0	0	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	59712	2	1	3	4	1	3	4	3	3	9	-1	auto	19.8 MiB	0.00	4	58.3 MiB	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.00	6.699e-06	3.697e-06	7.127e-05	5.3825e-05	2	2	2	53894	53894	1165.58	129.509	0.00	0.000173915	0.000126393	2	2	3	3	69	44	0.577715	0.577715	-0.9588	-0.577715	0	0	1165.58	129.509	0.00	0.00	8.1899e-05	6.0762e-05	
+k6_N10_mem32K_40nm.xml	single_ff.v	common_--reorder_rr_graph_nodes_algorithm_random_shuffle	0.42	vpr	58.44 MiB		0.01	5628	-1	-1	1	0.01	-1	-1	29204	-1	-1	1	2	0	0	success	v8.0.0-6591-g30d05496f-dirty	release VTR_ASSERT_LEVEL=2	GNU 7.5.0 on Linux-4.15.0-167-generic x86_64	2022-10-31T11:03:21	betzgrp-wintermute.eecg.utoronto.ca	/home/mahmo494/Desktop/centroid_placement_final/vtr-verilog-to-routing/vtr_flow/tasks	59844	2	1	3	4	1	3	4	3	3	9	-1	auto	19.9 MiB	0.00	4	58.4 MiB	0.00	0.00	0.570641	-0.944653	-0.570641	0.570641	0.00	5.617e-06	3.12e-06	5.5983e-05	4.034e-05	2	2	2	53894	53894	1165.58	129.509	0.00	0.00019837	0.000128497	2	2	3	3	69	44	0.577715	0.577715	-0.9588	-0.577715	0	0	1165.58	129.509	0.00	0.00	8.3083e-05	6.1534e-05