vpr: base: netlist writer: change access specifiers

Change access specifiers from private to protected
for some members of NetlistWriterVisitor to make those visible
in class that will derive from the visitor.

Signed-off-by: Pawel Czarnecki <[email protected]>

Author: lpawelcz

vpr/src/base/netlist_writer.cpp

@@ -883,7 +883,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
         print_sdf();
     }
 
-  private: //Internal Helper functions
+  protected: //Internal Helper functions
     ///@brief Writes out the verilog netlist
     void print_verilog(int depth = 0) {
         verilog_os_ << indent(depth) << "//Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n";
@@ -957,6 +957,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
         verilog_os_ << indent(depth) << "endmodule\n";
     }
 
+  private: //Internal Helper functions
     ///@brief Writes out the blif netlist
     void print_blif(int depth = 0) {
         blif_os_ << indent(depth) << "#BLIF generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n";
@@ -1061,47 +1062,6 @@ class NetlistWriterVisitor : public NetlistVisitor {
         sdf_os_ << indent(depth) << ")\n";
     }
 
-    /**
-     * @brief Returns the name of a wire connecting a primitive and global net.
-     *
-     * The wire is recorded and instantiated by the top level output routines.
-     */
-    std::string make_inst_wire(AtomNetId atom_net_id,  ///<The id of the net in the atom netlist
-                               tatum::NodeId tnode_id, ///<The tnode associated with the primitive pin
-                               std::string inst_name,  ///<The name of the instance associated with the pin
-                               PortType port_type,     ///<The port direction
-                               int port_idx,           ///<The instance port index
-                               int pin_idx) {          ///<The instance pin index
-
-        std::string wire_name = inst_name;
-        if (port_type == PortType::INPUT) {
-            wire_name = join_identifier(wire_name, "input");
-        } else if (port_type == PortType::CLOCK) {
-            wire_name = join_identifier(wire_name, "clock");
-        } else {
-            VTR_ASSERT(port_type == PortType::OUTPUT);
-            wire_name = join_identifier(wire_name, "output");
-        }
-
-        wire_name = join_identifier(wire_name, std::to_string(port_idx));
-        wire_name = join_identifier(wire_name, std::to_string(pin_idx));
-
-        auto value = std::make_pair(wire_name, tnode_id);
-        if (port_type == PortType::INPUT || port_type == PortType::CLOCK) {
-            //Add the sink
-            logical_net_sinks_[atom_net_id].push_back(value);
-
-        } else {
-            //Add the driver
-            VTR_ASSERT(port_type == PortType::OUTPUT);
-
-            auto ret = logical_net_drivers_.insert(std::make_pair(atom_net_id, value));
-            VTR_ASSERT(ret.second); //Was inserted, drivers are unique
-        }
-
-        return wire_name;
-    }
-
     /**
      * @brief Returns the name of a circuit-level Input/Output
      *
@@ -1157,6 +1117,48 @@ class NetlistWriterVisitor : public NetlistVisitor {
         return io_name;
     }
 
+  protected:
+    /**
+     * @brief Returns the name of a wire connecting a primitive and global net.
+     *
+     * The wire is recorded and instantiated by the top level output routines.
+     */
+    std::string make_inst_wire(AtomNetId atom_net_id,  ///<The id of the net in the atom netlist
+                               tatum::NodeId tnode_id, ///<The tnode associated with the primitive pin
+                               std::string inst_name,  ///<The name of the instance associated with the pin
+                               PortType port_type,     ///<The port direction
+                               int port_idx,           ///<The instance port index
+                               int pin_idx) {          ///<The instance pin index
+
+        std::string wire_name = inst_name;
+        if (port_type == PortType::INPUT) {
+            wire_name = join_identifier(wire_name, "input");
+        } else if (port_type == PortType::CLOCK) {
+            wire_name = join_identifier(wire_name, "clock");
+        } else {
+            VTR_ASSERT(port_type == PortType::OUTPUT);
+            wire_name = join_identifier(wire_name, "output");
+        }
+
+        wire_name = join_identifier(wire_name, std::to_string(port_idx));
+        wire_name = join_identifier(wire_name, std::to_string(pin_idx));
+
+        auto value = std::make_pair(wire_name, tnode_id);
+        if (port_type == PortType::INPUT || port_type == PortType::CLOCK) {
+            //Add the sink
+            logical_net_sinks_[atom_net_id].push_back(value);
+
+        } else {
+            //Add the driver
+            VTR_ASSERT(port_type == PortType::OUTPUT);
+
+            auto ret = logical_net_drivers_.insert(std::make_pair(atom_net_id, value));
+            VTR_ASSERT(ret.second); //Was inserted, drivers are unique
+        }
+
+        return wire_name;
+    }
+
     ///@brief Returns an Instance object representing the LUT
     std::shared_ptr<Instance> make_lut_instance(const t_pb* atom) {
         //Determine what size LUT
@@ -1772,18 +1774,6 @@ class NetlistWriterVisitor : public NetlistVisitor {
         return top_pb->pb_route;
     }
 
-    ///@brief Returns the top complex block which contains the given pb
-    const t_pb* find_top_cb(const t_pb* curr) {
-        //Walk up through the pb graph until curr
-        //has no parent, at which point it will be the top pb
-        const t_pb* parent = curr->parent_pb;
-        while (parent != nullptr) {
-            curr = parent;
-            parent = curr->parent_pb;
-        }
-        return curr;
-    }
-
     ///@brief Returns the tnode ID of the given atom's connected cluster pin
     tatum::NodeId find_tnode(const t_pb* atom, int cluster_pin_idx) {
         auto& atom_ctx = g_vpr_ctx.atom();
@@ -1801,6 +1791,19 @@ class NetlistWriterVisitor : public NetlistVisitor {
         return tnode_id;
     }
 
+  private:
+    ///@brief Returns the top complex block which contains the given pb
+    const t_pb* find_top_cb(const t_pb* curr) {
+        //Walk up through the pb graph until curr
+        //has no parent, at which point it will be the top pb
+        const t_pb* parent = curr->parent_pb;
+        while (parent != nullptr) {
+            curr = parent;
+            parent = curr->parent_pb;
+        }
+        return curr;
+    }
+
     ///@brief Returns a LogicVec representing the LUT mask of the given LUT atom
     LogicVec load_lut_mask(size_t num_inputs,  //LUT size
                            const t_pb* atom) { //LUT primitive
@@ -2058,13 +2061,15 @@ class NetlistWriterVisitor : public NetlistVisitor {
         return ::get_delay_ps(delay_sec); //Class overload hides file-scope by default
     }
 
-  private:                                                  //Data
-    std::string top_module_name_;                           ///<Name of the top level module (i.e. the circuit)
+  private:                        //Data
+    std::string top_module_name_; ///<Name of the top level module (i.e. the circuit)
+  protected:
     std::vector<std::string> inputs_;                       ///<Name of circuit inputs
     std::vector<std::string> outputs_;                      ///<Name of circuit outputs
     std::vector<Assignment> assignments_;                   ///<Set of assignments (i.e. net-to-net connections)
     std::vector<std::shared_ptr<Instance>> cell_instances_; ///<Set of cell instances
 
+  private:
     //Drivers of logical nets.
     // Key: logic net id, Value: pair of wire_name and tnode_id
     std::map<AtomNetId, std::pair<std::string, tatum::NodeId>> logical_net_drivers_;
@@ -2075,7 +2080,10 @@ class NetlistWriterVisitor : public NetlistVisitor {
     std::map<std::string, float> logical_net_sink_delays_;
 
     //Output streams
+  protected:
     std::ostream& verilog_os_;
+
+  private:
     std::ostream& blif_os_;
     std::ostream& sdf_os_;