Skip to content

Commit 904d190

Browse files
kimiatkhkimiatkh
committed
Fix the regression test for routing constraints
1 parent ff06e15 commit 904d190

File tree

3 files changed

+11
-10
lines changed

3 files changed

+11
-10
lines changed

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/config.txt

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ archs_dir=arch/
1010

1111
# Add circuits to list to sweep
1212
circuit_list_add=verilog/multiclock_output_and_latch.v
13-
circuit_list_add=verilog/multiclock_reader_writer.v
13+
circuit_list_add=verilog/and_latch.v
1414

1515
# Add architectures to list to sweep
1616
arch_list_add=timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml
@@ -32,4 +32,5 @@ qor_parse_file=qor_standard.txt
3232
pass_requirements_file=pass_requirements_clock_modeling.txt
3333

3434
# Script parameters
35-
script_params_list_add= --two_stage_clock_routing -read_vpr_constraints tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml
35+
# Since the used benchmarks in this test are small, a small target_utilization has been set to that the created grid is large enough for the clock network to get built properly
36+
script_params_list_add= --target_utilization 0.01 --two_stage_clock_routing -read_vpr_constraints tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml --clock_modeling dedicated_network

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets
2-
timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.96 vpr 62.98 MiB -1 -1 0.09 17312 1 0.06 -1 -1 32012 -1 -1 2 6 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64488 6 1 16 17 2 10 9 4 4 16 clb auto 24.4 MiB 0.01 17 27 11 11 5 63.0 MiB 0.00 0.00 0.876768 -3.49779 -0.876768 0.805 0.01 3.1307e-05 2.4383e-05 0.00025701 0.000223838 20 20 4 107788 107788 10441.3 652.579 0.03 0.00264684 0.0022844 750 1675 -1 16 2 9 9 138 81 0 0 138 81 9 9 0 0 21 14 0 0 22 21 0 0 9 9 0 0 47 16 0 0 30 12 0 0 9 0 0 0 0 0 9 0 0 1.18166 0.805 -4.08984 -1.18166 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00123192 0.0011725 3 7
3-
timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_reader_writer.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.99 vpr 63.57 MiB -1 -1 0.13 17352 1 0.05 -1 -1 31956 -1 -1 2 3 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 65092 3 -1 37 33 2 5 5 4 4 16 clb auto 25.1 MiB 0.01 2 12 2 3 7 63.6 MiB 0.00 0.00 1.45 -12.415 -1.45 1.45 0.01 7.4157e-05 6.5884e-05 0.00073152 0.000685799 8 1 1 107788 107788 4888.88 305.555 0.03 0.00414727 0.00381017 630 907 -1 1 1 1 1 10 6 0 0 10 6 1 1 0 0 2 1 0 0 2 2 0 0 1 1 0 0 3 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1.45 1.45 -12.4256 -1.45 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00230166 0.00221666 4 1
4-
timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.94 vpr 63.10 MiB -1 -1 0.11 17224 1 0.04 -1 -1 32076 -1 -1 2 6 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64612 6 1 16 17 2 10 9 4 4 16 clb auto 24.5 MiB 0.01 17 27 11 11 5 63.1 MiB 0.00 0.00 0.876768 -3.49779 -0.876768 0.805 0.01 3.0833e-05 2.4016e-05 0.00026753 0.000229748 20 20 4 107788 107788 10441.3 652.579 0.03 0.00264032 0.00227948 750 1675 -1 16 2 9 9 138 81 0 0 138 81 9 9 0 0 21 14 0 0 22 21 0 0 9 9 0 0 47 16 0 0 30 12 0 0 9 0 0 0 0 0 9 0 0 1.18166 0.805 -4.08984 -1.18166 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00130013 0.00124058 3 7
5-
timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_reader_writer.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 1.05 vpr 63.22 MiB -1 -1 0.12 17316 1 0.07 -1 -1 31904 -1 -1 2 3 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64736 3 -1 37 33 2 5 5 4 4 16 clb auto 24.7 MiB 0.01 2 12 2 3 7 63.2 MiB 0.00 0.00 1.45 -12.415 -1.45 1.45 0.01 7.3744e-05 6.5654e-05 0.000749719 0.000704822 8 1 1 107788 107788 4888.88 305.555 0.04 0.00597601 0.0053587 630 907 -1 1 1 1 1 10 6 0 0 10 6 1 1 0 0 2 1 0 0 2 2 0 0 1 1 0 0 3 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1.45 1.45 -12.4256 -1.45 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00228134 0.00219433 4 1
6-
timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.95 vpr 62.97 MiB -1 -1 0.09 17304 1 0.04 -1 -1 32016 -1 -1 2 6 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64480 6 1 16 17 2 10 9 4 4 16 clb auto 24.4 MiB 0.01 17 27 11 11 5 63.0 MiB 0.00 0.00 0.876768 -3.49779 -0.876768 0.805 0.01 4.2225e-05 3.2683e-05 0.000268149 0.00023055 20 20 4 107788 107788 10441.3 652.579 0.03 0.00272828 0.00235235 750 1675 -1 16 2 9 9 138 81 0 0 138 81 9 9 0 0 21 14 0 0 22 21 0 0 9 9 0 0 47 16 0 0 30 12 0 0 9 0 0 0 0 0 9 0 0 1.18166 0.805 -4.08984 -1.18166 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00127069 0.00121218 3 7
7-
timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_reader_writer.v common_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml 0.96 vpr 63.20 MiB -1 -1 0.11 17440 1 0.04 -1 -1 31944 -1 -1 2 3 0 0 success v8.0.0-9188-g9c862ec87-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-11-29T23:35:54 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 64712 3 -1 37 33 2 5 5 4 4 16 clb auto 24.6 MiB 0.01 2 12 2 3 7 63.2 MiB 0.00 0.00 1.45 -12.415 -1.45 1.45 0.01 7.268e-05 6.4675e-05 0.000730213 0.000686149 8 1 1 107788 107788 4888.88 305.555 0.03 0.00422287 0.00388435 630 907 -1 1 1 1 1 10 6 0 0 10 6 1 1 0 0 2 1 0 0 2 2 0 0 1 1 0 0 3 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1.45 1.45 -12.4256 -1.45 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00231144 0.00222596 4 1
1+
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets
2+
timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 74.18 vpr 67.70 MiB -1 -1 0.14 17128 1 0.05 -1 -1 32144 -1 -1 2 6 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69324 6 1 16 17 2 10 9 17 17 289 -1 auto 29.2 MiB 0.10 67 27 9 18 0 67.7 MiB 0.01 0.00 1.66771 -4.34981 -1.66771 0.805 14.84 0.000465591 0.000362362 0.00280543 0.00236583 20 141 4 1.34605e+07 107788 411619. 1424.29 33.41 0.0222166 0.0183417 24098 82050 -1 132 2 10 10 10345 2735 2.73969 0.805 -5.54288 -2.73969 -0.842296 -0.421627 535376. 1852.51 3.02 4.92 1.80 -1 -1 3.02 0.00712665 0.00644851 1 9
3+
timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 39.92 vpr 67.36 MiB -1 -1 0.12 16896 1 0.02 -1 -1 29976 -1 -1 1 3 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68972 3 1 5 6 1 4 5 13 13 169 -1 auto 28.9 MiB 0.03 26 12 4 8 0 67.4 MiB 0.01 0.00 0.684768 -1.31529 -0.684768 0.684768 7.66 0.000145249 0.000107804 0.000912111 0.000756221 20 52 1 6.63067e+06 53894 227243. 1344.63 17.97 0.00522005 0.00428397 13251 44387 -1 54 1 4 4 4093 1283 1.57879 1.57879 -1.64658 -1.57879 -0.385237 -0.385237 294987. 1745.49 1.62 2.64 0.97 -1 -1 1.62 0.00213645 0.00194794 0 4
4+
timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 75.45 vpr 67.44 MiB -1 -1 0.13 17128 1 0.05 -1 -1 32000 -1 -1 2 6 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69056 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.10 86 27 10 16 1 67.4 MiB 0.01 0.00 1.73508 -4.45965 -1.73508 0.805 14.86 0.000467564 0.000363489 0.00253116 0.00209264 20 156 3 1.34605e+07 107788 424167. 1467.71 34.10 0.0264007 0.0217019 24098 84646 -1 143 1 9 9 10051 2608 2.60696 0.805 -5.45498 -2.60696 -0.46436 -0.232734 547923. 1895.93 3.00 4.91 1.82 -1 -1 3.00 0.0058344 0.00529701 1 9
5+
timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 40.03 vpr 67.21 MiB -1 -1 0.12 17012 1 0.02 -1 -1 29904 -1 -1 1 3 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 68828 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.03 26 12 4 8 0 67.2 MiB 0.01 0.00 0.698051 -1.3327 -0.698051 0.698051 7.93 0.000142967 0.00010535 0.000901405 0.000744567 20 52 1 6.63067e+06 53894 235789. 1395.20 18.41 0.00525922 0.0042924 13251 46155 -1 54 1 4 4 4037 1263 1.58964 1.58964 -1.65632 -1.58964 -0.386343 -0.386343 303533. 1796.05 1.66 2.71 1.01 -1 -1 1.66 0.00212216 0.00193398 0 4
6+
timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 74.59 vpr 67.81 MiB -1 -1 0.14 16948 1 0.05 -1 -1 32132 -1 -1 2 6 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69440 6 1 16 17 2 10 9 17 17 289 -1 auto 29.2 MiB 0.10 67 27 9 18 0 67.8 MiB 0.01 0.00 1.66771 -4.34981 -1.66771 0.805 14.86 0.00046856 0.000365172 0.00281248 0.00237262 20 619 3 1.34605e+07 107788 408865. 1414.76 33.53 0.0204852 0.0169571 24098 82150 -1 610 2 10 10 12597 4156 3.681 0.805 -7.42729 -3.681 -2.7249 -1.36293 532630. 1843.01 3.06 4.99 1.80 -1 -1 3.06 0.00669788 0.00599603 1 9
7+
timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 39.06 vpr 67.42 MiB -1 -1 0.12 16968 1 0.02 -1 -1 29828 -1 -1 1 3 0 0 success v8.0.0-10222-gff06e159c-dirty debug VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2024-06-02T14:52:40 betzgrp-wintermute.eecg.utoronto.ca /home/talaeikh/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 69036 3 1 5 6 1 4 5 13 13 169 -1 auto 28.9 MiB 0.03 26 12 4 8 0 67.4 MiB 0.01 0.00 0.684768 -1.31529 -0.684768 0.684768 7.60 0.000142626 0.000105207 0.000839515 0.000682556 20 183 1 6.63067e+06 53894 225153. 1332.26 17.38 0.00516117 0.00422186 13251 44463 -1 185 1 4 4 1139 237 2.19802 2.19802 -2.19802 -2.19802 -1.00447 -1.00447 292904. 1733.16 1.53 2.55 0.98 -1 -1 1.53 0.00214788 0.00195713 0 4

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
<vpr_constraints>
22
<global_route_constraints>
3-
<set_global_signal name="clock*" network_name="clock_network" route_model="dedicated_network"/>
3+
<set_global_signal name="clock.*" network_name="clock_network" route_model="dedicated_network"/>
44
</global_route_constraints>
55
</vpr_constraints>

0 commit comments

Comments
 (0)