Merge branch 'master' into 3d_link_cost_in_placement

Author: amin1377

.github/workflows/test.yml

@@ -26,22 +26,23 @@ jobs:
       fail-fast: false
       matrix:
         include:
-          - {test: "vtr_reg_nightly_test1",      cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "",          cmake: "-DWITH_PARMYS=OFF -DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test2",      cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "",          cmake: "-DWITH_PARMYS=OFF -DWITH_ODIN=ON",                                               extra_pkgs: "" }
-          - {test: "vtr_reg_nightly_test3",      cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test3_odin", cores: "16", options: "",          cmake: "-DWITH_PARMYS=OFF -DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test4",      cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: "" }
-          - {test: "vtr_reg_nightly_test4_odin", cores: "16", options: "",          cmake: "-DWITH_PARMYS=OFF -DWITH_ODIN=ON",                                               extra_pkgs: "" }
-          - {test: "vtr_reg_nightly_test5",      cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: ""}
-          - {test: "vtr_reg_nightly_test6",      cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: ""}
-          - {test: "vtr_reg_parmys",             cores: "16", options: "",          cmake: "",                                                                               extra_pkgs: "" }
-          - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                                           extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_PARMYS=OFF -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_PARMYS=OFF -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                                       extra_pkgs: ""}
-          - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_PARMYS=OFF -DWITH_ODIN=ON",                                               extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test1",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test2",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: "" }
+          - {test: "vtr_reg_nightly_test3",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test3_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test4",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: "" }
+          - {test: "vtr_reg_nightly_test4_odin", cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: "" }
+          - {test: "vtr_reg_nightly_test5",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test6",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
+          - {test: "vtr_reg_nightly_test7",      cores: "16", options: "",          cmake: "",                                                             extra_pkgs: ""}
+          - {test: "vtr_reg_parmys",             cores: "16", options: "",          cmake: "",                                                             extra_pkgs: "" }
+          - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
+          - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
+          - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
+          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""}
+          - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

README.developers.md

@@ -222,31 +222,28 @@ Its primary purpose is try and achieve high functionality coverage.
 QoR checks in this regression test are primarily 'canary' checks to catch gross degradations in QoR.
 Occasionally, changes can cause QoR failures (e.g. due to CAD noise -- particularly on small benchmarks); usually such failures are not a concern if the QoR differences are small.
 
-### vtr_reg_nightly_test1-3
+### vtr_reg_nightly_test1-N
 
-**Goal:** Basic QoR and Performance evaluation 
+**Goal:** Most QoR and Performance evaluation 
 
 **Feature Coverage:** Medium
 
 **Architectures:** A wider variety of architectures
 
-**Benchmarks:** Small-medium size, diverse. All include: 
+**Benchmarks:** Small-large size, diverse. Includes: 
 
 * VTR benchmarks
-* Additional benchmarks for each suite. 
+* Titan benchmarks except gaussian_blur (which has the longest run time)
+* Koios benchmarks
+* Various special benchmarks and tests for functionality 
 
    QoR checks in these regression suites are aimed at evaluating quality and run-time of the VTR flow.
    As a result any QoR failures are a concern and should be investigated and understood.
 
    Note:
 
-   These suites comproise a single large suite, `vtr_reg_nightly` and should be run together to test nightly level regression. They are mostly similar in benchmark coverage interms of size and diversity however each suite tests some unique benchmarks in addition to the VTR benchmarks.  
+   These suites comprise a single large suite, `vtr_reg_nightly` and should be run together to test nightly level regression. They are mostly similar in benchmark coverage interms of size and diversity however each suite tests some unique benchmarks in addition to the VTR benchmarks. Each vtr_reg_nightly<N> suite runs on a different server (in parallel), so by having N such test suites we speed up CI by a factor of N. Currently the runtime of each suite is capped at 6 hours, so if the runtime exceeds six hours a new vtr_reg_nightly suite (i.e. N+1) should be created.
 
-    | suite | wall-clock time| Additional benchmarks|
-    |-------|----------------|----------------------|
-    |vtr_reg_nightly_test1|~4.5 hours with `-j8`|ISPD and MCNC20 |
-    |vtr_reg_nightly_test2|~6 hours with `-j8`|Titan23 and Titan `other`|
-    |vtr_reg_nightly_test3|~5.5 hours with `-j8`|none|
 
 ### vtr_reg_weekly
 
@@ -259,7 +256,7 @@ Occasionally, changes can cause QoR failures (e.g. due to CAD noise -- particula
 **Benchmarks:** Medium-Large size, diverse. Includes:
 
 * VTR benchmarks
-* Titan23 benchmarks
+* Titan23 benchmarks, including gaussian_blur
 
 **Architectures:** A wide variety of architectures
 
@@ -306,11 +303,12 @@ a Slurm-managed cluster can be found under vtr_flow/tasks/slurm/
 ## Continuous integration (CI)
 For the following tests, you can use remote servers instead of running them locally. Once the changes are pushed into the 
 remote repository, or a PR is created, the [Test Workflow](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/.github/workflows/test.yml)
-will be triggered. The following tests are included in the workflow:
-* [vtr_reg_nightly_test1-3](#vtr_reg_nightly_test1-3)
+will be triggered. Many tests are included in the workflow, including:
+* [vtr_reg_nightly_test1-N](#vtr_reg_nightly_test1-N)
 * [vtr_reg_strong](#vtr_reg_strong)
-* parmys_reg_basic
+* [vtr_reg_basic](#vtr_reg_basic)
 * odin_reg_strong
+* parmys_reg_basic
 
 instructions on how to gather QoR results of CI runs can be found [here](#example-extracting-qor-data-from-ci-runs).
 

doc/src/vpr/command_line_usage.rst

@@ -800,7 +800,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
     **Default:** ``0.0``
 
 .. _dusty_sa_options:
-Setting any of the following options selects `Dusty's annealing schedule <dusty_sa.rst>`_.
+Setting any of the following 5 options selects :ref:`Dusty's annealing schedule <dusty_sa>` .
 
 .. option:: --alpha_min <float>
 
@@ -954,6 +954,13 @@ The following options are only valid when the placement engine is in timing-driv
 
     **Default:** ``0``
 
+.. option:: --quench_recompute_divider <int>
+
+    Controls how many times the placer performs a timing analysis to update its criticality estimates during a quench. 
+    If unspecified, uses the value from --inner_loop_recompute_divider.
+
+    **Default:** ``0``
+
 .. option:: --td_place_exp_first <float>
 
     Controls how critical a connection is considered as a function of its slack, at the start of the anneal.

doc/src/vpr/dusty_sa.rst

@@ -1,3 +1,5 @@
+.. _dusty_sa:
+
 Dusty's Simulated Annealing Schedule
 ====================================
 

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt

@@ -2,15 +2,12 @@ regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer
 regression_tests/vtr_reg_nightly_test2/vtr_func_formal 
 regression_tests/vtr_reg_nightly_test2/vtr_bidir 
 regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph
-regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_flat_router
-regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir  
+regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir
 regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch 
 regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan
 regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check
-#regression_tests/vtr_reg_nightly_test2/vpr_verify_router_lookahead_flat_router @TODO: fix this test
-regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff 
+regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff
 regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan
 regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc
 regression_tests/vtr_reg_nightly_test2/titan_other
-regression_tests/vtr_reg_nightly_test2/titan_other_flat_router
 regression_tests/vtr_reg_nightly_test2/titan_quick_qor

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt

@@ -1,6 +1,5 @@
 regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain
 regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop
-regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop_flat_router
 regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off
 regression_tests/vtr_reg_nightly_test3/vtr_reg_qor
-regression_tests/vtr_reg_nightly_test3/complex_switch
+regression_tests/vtr_reg_nightly_test3/complex_switch

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt

@@ -0,0 +1,5 @@
+regression_tests/vtr_reg_nightly_test7/titan_other_run_flat
+#regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat
+#regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat
+#regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat
+regression_tests/vtr_reg_nightly_test7/verify_rr_graph_run_flat

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other_flat_router/config/config.txt renamed to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/config.txt

@@ -0,0 +1,34 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=bgm.v
+circuit_list_add=LU8PEEng.v
+circuit_list_add=LU32PEEng.v
+circuit_list_add=mcml.v
+circuit_list_add=stereovision0.v
+circuit_list_add=stereovision1.v
+circuit_list_add=stereovision2.v
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_large.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -max_router_iterations 300 --flat_routing true