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flow: Add regression test for reconvergent routing
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##############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/verilog
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# Path to directory of architectures to use
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archs_dir=arch/timing
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# Add circuits to list to sweep
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circuit_list_add=mkSMAdapter4B.v
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# Add architectures to list to sweep
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arch_list_add=k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
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# Parse info and how to parse
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parse_file=vpr_standard.txt
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# How to parse QoR info
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qor_parse_file=qor_standard.txt
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# Pass requirements
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pass_requirements_file=pass_requirements.txt
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# Script parameters
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script_params= -track_memory_usage --router_max_convergence_count 3
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
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k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 16.99 0.18 28888 4 1.57 -1 -1 38300 -1 -1 172 193 5 0 v8.0.0-rc1-790-g827f8f171 success 95828 193 205 2926 2852 1 1390 575 20 20 400 memory auto 1.37 10843 2.23 4.46039 -2528.56 -4.46039 86 21461 33 2.07112e+07 1.20098e+07 2.25044e+06 5626.10 9.03 19475 17 4849 13655 1585934 346179 4.75183 -2850.08 -4.75183 -8.02468 -0.339827 2.83111e+06 7077.77 0.49

vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

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regression_tests/vtr_reg_strong/strong_global_nonuniform
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regression_tests/vtr_reg_strong/strong_sdc
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regression_tests/vtr_reg_strong/strong_timing_report_detail
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regression_tests/vtr_reg_strong/strong_route_reconverge

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