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vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config
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lines changed Original file line number Diff line number Diff line change 1- arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.54 vpr 54.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5 .0 on Linux-4.15 .0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 55800 1 4 28 32 2 10 9 4 4 16 clb auto 15.8 MiB 0.03 20 54.5 MiB 0.00 0.00 2.18276 0 0 2.18276 0.02 2.9141e -05 2.1776e -05 0.000384601 0.00034525 8 18 4 215576 215576 5503.53 343.971 0.03 0.00411474 0.00340189 12 4 18 18 422 145 2.20417 2.20417 0 0 0 0 6317.10 394.819 0.00 0.00 0.000888863 0.000804989
3- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.66 vpr 54.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5 .0 on Linux-4.15 .0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56048 1 4 28 32 2 10 9 4 4 16 clb auto 15.9 MiB 0.02 20 54.7 MiB 0.03 0.00 2.18276 0 0 2.18276 0.02 5.182e -05 4.0804e -05 0.000410032 0.000361391 8 18 4 215576 215576 5503.53 343.971 0.06 0.00413673 0.00341089 12 4 18 18 422 145 2.20417 2.20417 0 0 0 0 6317.10 394.819 0.00 0.00 0.000908048 0.000820443
4- timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.57 vpr 54.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5 .0 on Linux-4.15 .0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 56080 1 4 28 32 2 10 9 4 4 16 clb auto 15.9 MiB 0.01 20 54.8 MiB 0.00 0.00 2.18276 0 0 2.18276 0.01 2.5851e -05 1.9164e -05 0.000325142 0.000288851 8 18 4 215576 215576 5503.53 343.971 0.03 0.0040566 0.00334035 12 4 18 18 422 145 2.20417 2.20417 0 0 0 0 6317.10 394.819 0.01 0.00 0.00112307 0.0010329
1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.15 vpr 57.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 -1 782a17c Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.5 .0-1025-azure x86_64 2024-08-16T12:48:04 -1 -1 59008 1 4 28 32 2 10 9 4 4 16 clb auto 19.2 MiB 0.00 20 27 15 8 4 57.6 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 3.6649e -05 3.0788e -05 0.000332461 0.000302474 8 12 5 72000 72000 5593.62 349.601 0.01 0.00463095 0.00390158 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00184241 0.00173742
3+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.15 vpr 57.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 -1 782a17c Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.5 .0-1025-azure x86_64 2024-08-16T12:48:04 -1 -1 58880 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 20 27 15 8 4 57.5 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 3.6368e -05 3.0868e -05 0.000334423 0.000304918 8 12 5 72000 72000 5593.62 349.601 0.01 0.00434957 0.00368628 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00187403 0.00175995
4+ timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.15 vpr 57.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 -1 782a17c Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4 .0 on Linux-6.5 .0-1025-azure x86_64 2024-08-16T12:48:04 -1 -1 58748 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 20 27 15 8 4 57.4 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 3.6097e -05 3.0537e -05 0.000332419 0.000303054 8 12 5 72000 72000 5593.62 349.601 0.01 0.00433458 0.00365113 672 1128 -1 12 6 24 24 485 152 2.38921 2.38921 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00181848 0.00171448
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