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Merge pull request #1812 from verilog-to-routing/mixing_optimization_typo
[Odin]: fix arch name type for mixing optimization tasks in Odin regtest
2 parents dd7fd42 + 8d5eda9 commit 8b2d0ed

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12 files changed

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‎ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json

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@@ -337,6 +337,366 @@
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"Estimated LUTs": 21,
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"Total Node": 26
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},
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"config_file_half/bm_base_multiply/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_base_multiply/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "bm_base_multiply.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 11.6,
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"exec_time(ms)": 560.3,
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"simulation_time(ms)": 538.1,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 47,
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"Po": 78,
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"logic element": 454,
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"latch": 71,
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"Multiplier": 1,
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"generic logic size": 5,
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"Longest Path": 25,
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"Average Path": 5,
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"Estimated LUTs": 454,
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"Total Node": 527
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},
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"config_file_half/bm_base_multiply/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_base_multiply/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "bm_base_multiply.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 11.7,
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"exec_time(ms)": 569.7,
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"simulation_time(ms)": 540.2,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 47,
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"Po": 78,
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"logic element": 454,
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"latch": 71,
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"Multiplier": 1,
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"generic logic size": 6,
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"Longest Path": 25,
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"Average Path": 5,
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"Estimated LUTs": 454,
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"Total Node": 527
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},
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"config_file_half/bm_match1_str_arch/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match1_str_arch/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "bm_match1_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 13.7,
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"exec_time(ms)": 1869.4,
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"simulation_time(ms)": 1821.2,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 88,
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"Po": 144,
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"logic element": 1775,
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"latch": 72,
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"Multiplier": 1,
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"generic logic size": 5,
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"Longest Path": 74,
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"Average Path": 5,
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"Estimated LUTs": 1775,
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"Total Node": 1849
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},
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"config_file_half/bm_match1_str_arch/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match1_str_arch/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "bm_match1_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 13.9,
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"exec_time(ms)": 1823.8,
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"simulation_time(ms)": 1775.1,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 88,
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"Po": 144,
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"logic element": 1775,
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"latch": 72,
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"Multiplier": 1,
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"generic logic size": 6,
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"Longest Path": 74,
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"Average Path": 5,
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"Estimated LUTs": 1775,
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"Total Node": 1849
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},
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"config_file_half/bm_match2_str_arch/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match2_str_arch/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "bm_match2_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 12.5,
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"exec_time(ms)": 924.5,
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"simulation_time(ms)": 886.5,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 99,
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"logic element": 881,
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"latch": 54,
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"Multiplier": 2,
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"generic logic size": 5,
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"Longest Path": 31,
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"Average Path": 6,
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"Estimated LUTs": 881,
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"Total Node": 938
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},
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"config_file_half/bm_match2_str_arch/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match2_str_arch/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "bm_match2_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 12.5,
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"exec_time(ms)": 906,
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"simulation_time(ms)": 872.3,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 99,
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"logic element": 881,
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"latch": 54,
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"Multiplier": 2,
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"generic logic size": 6,
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"Longest Path": 31,
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"Average Path": 6,
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"Estimated LUTs": 881,
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"Total Node": 938
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},
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"config_file_half/bm_match3_str_arch/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match3_str_arch/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "bm_match3_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 9.5,
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"exec_time(ms)": 430.6,
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"simulation_time(ms)": 402.8,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 54,
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"logic element": 375,
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"latch": 54,
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"generic logic size": 5,
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"Longest Path": 58,
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"Average Path": 5,
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"Estimated LUTs": 375,
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"Total Node": 430
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},
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"config_file_half/bm_match3_str_arch/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match3_str_arch/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "bm_match3_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 9.7,
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"exec_time(ms)": 420.3,
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"simulation_time(ms)": 395.2,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 54,
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"Po": 54,
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"logic element": 375,
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"latch": 54,
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"generic logic size": 6,
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"Longest Path": 58,
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"Average Path": 5,
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"Estimated LUTs": 375,
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"Total Node": 430
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},
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"config_file_half/bm_match4_str_arch/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match4_str_arch/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "bm_match4_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 12.5,
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"exec_time(ms)": 968.2,
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"simulation_time(ms)": 928.9,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 51,
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"Po": 216,
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"logic element": 746,
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"latch": 108,
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"Multiplier": 1,
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"generic logic size": 5,
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"Longest Path": 48,
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"Average Path": 5,
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"Estimated LUTs": 746,
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"Total Node": 856
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},
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"config_file_half/bm_match4_str_arch/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match4_str_arch/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "bm_match4_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 12.4,
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"exec_time(ms)": 946,
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"simulation_time(ms)": 913.1,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 51,
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"Po": 216,
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"logic element": 746,
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"latch": 108,
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"Multiplier": 1,
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"generic logic size": 6,
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"Longest Path": 48,
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"Average Path": 5,
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"Estimated LUTs": 746,
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"Total Node": 856
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},
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"config_file_half/bm_match5_str_arch/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match5_str_arch/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "bm_match5_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 12.7,
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"exec_time(ms)": 1025.9,
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"simulation_time(ms)": 991.3,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 90,
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"Po": 54,
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"logic element": 982,
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"latch": 54,
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"Multiplier": 3,
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"generic logic size": 5,
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"Longest Path": 32,
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"Average Path": 5,
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"Estimated LUTs": 982,
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"Total Node": 1040
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},
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"config_file_half/bm_match5_str_arch/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/bm_match5_str_arch/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "bm_match5_str_arch.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 12.6,
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"exec_time(ms)": 849.3,
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"simulation_time(ms)": 814.4,
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"test_coverage(%)": 100,
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"Latch Drivers": 1,
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"Pi": 90,
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"Po": 54,
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"logic element": 982,
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"latch": 54,
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"Multiplier": 3,
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"generic logic size": 6,
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"Longest Path": 32,
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"Average Path": 5,
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"Estimated LUTs": 982,
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"Total Node": 1040
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},
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"config_file_half/multiply_hard_block/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/multiply_hard_block/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "multiply_hard_block.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 11.1,
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"exec_time(ms)": 29.4,
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"simulation_time(ms)": 8.8,
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"test_coverage(%)": 100,
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"Pi": 8,
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"Po": 8,
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"logic element": 17,
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"Multiplier": 1,
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"generic logic size": 5,
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"Longest Path": 7,
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"Average Path": 4,
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"Estimated LUTs": 17,
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"Total Node": 18
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},
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"config_file_half/multiply_hard_block/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/multiply_hard_block/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "multiply_hard_block.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 10.8,
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"exec_time(ms)": 29.1,
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"simulation_time(ms)": 9,
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"test_coverage(%)": 100,
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"Pi": 8,
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"Po": 8,
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"logic element": 17,
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"Multiplier": 1,
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"generic logic size": 6,
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"Longest Path": 7,
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"Average Path": 4,
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"Estimated LUTs": 17,
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"Total Node": 18
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},
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"config_file_half/twobits_arithmetic_multiply/k6_frac_N10_mem32K_40nm": {
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"test_name": "config_file_half/twobits_arithmetic_multiply/k6_frac_N10_mem32K_40nm",
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"architecture": "k6_frac_N10_mem32K_40nm.xml",
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"blif": "twobits_arithmetic_multiply.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 9.2,
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"exec_time(ms)": 22.6,
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"simulation_time(ms)": 3.1,
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"test_coverage(%)": 92.5,
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"Latch Drivers": 1,
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"Pi": 5,
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"Po": 5,
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"logic element": 21,
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"latch": 4,
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"generic logic size": 5,
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"Longest Path": 9,
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"Average Path": 5,
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"Estimated LUTs": 21,
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"Total Node": 26
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},
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"config_file_half/twobits_arithmetic_multiply/k6_N10_mem32K_40nm": {
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"test_name": "config_file_half/twobits_arithmetic_multiply/k6_N10_mem32K_40nm",
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"architecture": "k6_N10_mem32K_40nm.xml",
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"blif": "twobits_arithmetic_multiply.blif",
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"warnings": [
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"[PARSE_ARGS] Must include only one of either:"
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],
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"max_rss(MiB)": 9.2,
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"exec_time(ms)": 16.2,
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"simulation_time(ms)": 2.5,
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"test_coverage(%)": 92.5,
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"Latch Drivers": 1,
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"Pi": 5,
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"Po": 5,
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"logic element": 21,
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"latch": 4,
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"generic logic size": 6,
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"Longest Path": 9,
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"Average Path": 5,
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"Estimated LUTs": 21,
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"Total Node": 26
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},
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"DEFAULT": {
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"test_name": "n/a",
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"architecture": "n/a",

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