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lines changed Original file line number Diff line number Diff line change @@ -395,11 +395,14 @@ jobs:
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CMAKE_PARAMS : ' -DSYNLIG_SYSTEMVERILOG=ON'
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NUM_PROC : ${{ steps.cpu-cores.outputs.count }}
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run : |
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- git submodule sync --recursive # Sync submodules
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- git submodule update --init --recursive # Ensure they are initialized & updated'
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export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
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./.github/scripts/build.sh
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./run_reg_test.py vtr_reg_system_verilog -show_failures -j${{ steps.cpu-cores.outputs.count}}
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+
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+ - name : Check Synlig Installation Path
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+ run : |
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+ echo "Checking installed Synlig binary..."
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+ ls -l /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing/build/bin/synlig_install/usr/local/bin/
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ODINII :
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name : ' ODIN-II Basic Test'
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